diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-30 16:54:10 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-30 16:54:10 -0500 |
| commit | 23e041dbaa80eb1032f9d612433c6b9062da5afd (patch) | |
| tree | 40783f4dff7c887e424c2466d7b74deb2c019a64 /drivers/gpu/drm/radeon | |
| parent | f50733450362182fd16d658751615635850a8bff (diff) | |
| parent | 5349ef3127c77075ff70b2014f17ae0fbcaaf199 (diff) | |
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/fb: fix FBIOGET/PUT_VSCREENINFO pixel clock handling
drm: make sure page protections are updated after changing vm_flags
drm/radeon/kms: Report vga connector is connected according to ddc_probe
drm: mm always protect change to unused_nodes with unused_lock spinlock
drm/radeon/kms: Disable TV load detect on RS400,RC410,RS480
drm/radeon/kms: read back register before writing in IIO.
drm/radeon/kms: fix handling of d1/d2 vga
drm: work around EDIDs with bad htotal/vtotal values
drm/radeon/kms: resume AGP by calling init.
Diffstat (limited to 'drivers/gpu/drm/radeon')
| -rw-r--r-- | drivers/gpu/drm/radeon/atom.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_agp.c | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_connectors.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/rv515.c | 9 |
6 files changed, 32 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c index 901befe03da2..d67c42555ab9 100644 --- a/drivers/gpu/drm/radeon/atom.c +++ b/drivers/gpu/drm/radeon/atom.c | |||
| @@ -107,6 +107,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base, | |||
| 107 | base += 3; | 107 | base += 3; |
| 108 | break; | 108 | break; |
| 109 | case ATOM_IIO_WRITE: | 109 | case ATOM_IIO_WRITE: |
| 110 | (void)ctx->card->reg_read(ctx->card, CU16(base + 1)); | ||
| 110 | ctx->card->reg_write(ctx->card, CU16(base + 1), temp); | 111 | ctx->card->reg_write(ctx->card, CU16(base + 1), temp); |
| 111 | base += 3; | 112 | base += 3; |
| 112 | break; | 113 | break; |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 757f5cd37744..224506a2f7b1 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
| @@ -519,6 +519,7 @@ typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |||
| 519 | * AGP | 519 | * AGP |
| 520 | */ | 520 | */ |
| 521 | int radeon_agp_init(struct radeon_device *rdev); | 521 | int radeon_agp_init(struct radeon_device *rdev); |
| 522 | void radeon_agp_resume(struct radeon_device *rdev); | ||
| 522 | void radeon_agp_fini(struct radeon_device *rdev); | 523 | void radeon_agp_fini(struct radeon_device *rdev); |
| 523 | 524 | ||
| 524 | 525 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c index 23ea9955ac59..54bf49a6d676 100644 --- a/drivers/gpu/drm/radeon/radeon_agp.c +++ b/drivers/gpu/drm/radeon/radeon_agp.c | |||
| @@ -237,6 +237,18 @@ int radeon_agp_init(struct radeon_device *rdev) | |||
| 237 | #endif | 237 | #endif |
| 238 | } | 238 | } |
| 239 | 239 | ||
| 240 | void radeon_agp_resume(struct radeon_device *rdev) | ||
| 241 | { | ||
| 242 | #if __OS_HAS_AGP | ||
| 243 | int r; | ||
| 244 | if (rdev->flags & RADEON_IS_AGP) { | ||
| 245 | r = radeon_agp_init(rdev); | ||
| 246 | if (r) | ||
| 247 | dev_warn(rdev->dev, "radeon AGP reinit failed\n"); | ||
| 248 | } | ||
| 249 | #endif | ||
| 250 | } | ||
| 251 | |||
| 240 | void radeon_agp_fini(struct radeon_device *rdev) | 252 | void radeon_agp_fini(struct radeon_device *rdev) |
| 241 | { | 253 | { |
| 242 | #if __OS_HAS_AGP | 254 | #if __OS_HAS_AGP |
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index fce4c4087fda..29763ceae3af 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c | |||
| @@ -566,8 +566,9 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect | |||
| 566 | radeon_i2c_do_lock(radeon_connector, 0); | 566 | radeon_i2c_do_lock(radeon_connector, 0); |
| 567 | 567 | ||
| 568 | if (!radeon_connector->edid) { | 568 | if (!radeon_connector->edid) { |
| 569 | DRM_ERROR("DDC responded but not EDID found for %s\n", | 569 | DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", |
| 570 | drm_get_connector_name(connector)); | 570 | drm_get_connector_name(connector)); |
| 571 | ret = connector_status_connected; | ||
| 571 | } else { | 572 | } else { |
| 572 | radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); | 573 | radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); |
| 573 | 574 | ||
| @@ -720,8 +721,8 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect | |||
| 720 | radeon_i2c_do_lock(radeon_connector, 0); | 721 | radeon_i2c_do_lock(radeon_connector, 0); |
| 721 | 722 | ||
| 722 | if (!radeon_connector->edid) { | 723 | if (!radeon_connector->edid) { |
| 723 | DRM_ERROR("DDC responded but not EDID found for %s\n", | 724 | DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", |
| 724 | drm_get_connector_name(connector)); | 725 | drm_get_connector_name(connector)); |
| 725 | } else { | 726 | } else { |
| 726 | radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); | 727 | radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); |
| 727 | 728 | ||
| @@ -1149,6 +1150,13 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
| 1149 | if (ret) | 1150 | if (ret) |
| 1150 | goto failed; | 1151 | goto failed; |
| 1151 | radeon_connector->dac_load_detect = true; | 1152 | radeon_connector->dac_load_detect = true; |
| 1153 | /* RS400,RC410,RS480 chipset seems to report a lot | ||
| 1154 | * of false positive on load detect, we haven't yet | ||
| 1155 | * found a way to make load detect reliable on those | ||
| 1156 | * chipset, thus just disable it for TV. | ||
| 1157 | */ | ||
| 1158 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) | ||
| 1159 | radeon_connector->dac_load_detect = false; | ||
| 1152 | drm_connector_attach_property(&radeon_connector->base, | 1160 | drm_connector_attach_property(&radeon_connector->base, |
| 1153 | rdev->mode_info.load_detect_property, | 1161 | rdev->mode_info.load_detect_property, |
| 1154 | 1); | 1162 | 1); |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index e3f9edfa40fe..41bb76fbe734 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
| @@ -688,6 +688,8 @@ int radeon_resume_kms(struct drm_device *dev) | |||
| 688 | return -1; | 688 | return -1; |
| 689 | } | 689 | } |
| 690 | pci_set_master(dev->pdev); | 690 | pci_set_master(dev->pdev); |
| 691 | /* resume AGP if in use */ | ||
| 692 | radeon_agp_resume(rdev); | ||
| 691 | radeon_resume(rdev); | 693 | radeon_resume(rdev); |
| 692 | radeon_restore_bios_scratch_regs(rdev); | 694 | radeon_restore_bios_scratch_regs(rdev); |
| 693 | fb_set_suspend(rdev->fbdev_info, 0); | 695 | fb_set_suspend(rdev->fbdev_info, 0); |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 7935f793bf62..ba68c9fe90a1 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
| @@ -137,8 +137,6 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev) | |||
| 137 | 137 | ||
| 138 | void rv515_vga_render_disable(struct radeon_device *rdev) | 138 | void rv515_vga_render_disable(struct radeon_device *rdev) |
| 139 | { | 139 | { |
| 140 | WREG32(R_000330_D1VGA_CONTROL, 0); | ||
| 141 | WREG32(R_000338_D2VGA_CONTROL, 0); | ||
| 142 | WREG32(R_000300_VGA_RENDER_CONTROL, | 140 | WREG32(R_000300_VGA_RENDER_CONTROL, |
| 143 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); | 141 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
| 144 | } | 142 | } |
| @@ -382,7 +380,6 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) | |||
| 382 | save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); | 380 | save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); |
| 383 | 381 | ||
| 384 | /* Stop all video */ | 382 | /* Stop all video */ |
| 385 | WREG32(R_000330_D1VGA_CONTROL, 0); | ||
| 386 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | 383 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
| 387 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); | 384 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
| 388 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); | 385 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
| @@ -391,6 +388,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) | |||
| 391 | WREG32(R_006880_D2CRTC_CONTROL, 0); | 388 | WREG32(R_006880_D2CRTC_CONTROL, 0); |
| 392 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); | 389 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
| 393 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | 390 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
| 391 | WREG32(R_000330_D1VGA_CONTROL, 0); | ||
| 392 | WREG32(R_000338_D2VGA_CONTROL, 0); | ||
| 394 | } | 393 | } |
| 395 | 394 | ||
| 396 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) | 395 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
| @@ -404,14 +403,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) | |||
| 404 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); | 403 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
| 405 | mdelay(1); | 404 | mdelay(1); |
| 406 | /* Restore video state */ | 405 | /* Restore video state */ |
| 406 | WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); | ||
| 407 | WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); | ||
| 407 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); | 408 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
| 408 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); | 409 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); |
| 409 | WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); | 410 | WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); |
| 410 | WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); | 411 | WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); |
| 411 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); | 412 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
| 412 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | 413 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
| 413 | WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); | ||
| 414 | WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); | ||
| 415 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); | 414 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
| 416 | } | 415 | } |
| 417 | 416 | ||
