diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2011-03-02 20:07:31 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-03-02 20:51:13 -0500 |
commit | 0c88a02ef6b7e29a811f0d56367cc2268c4ef433 (patch) | |
tree | d098334ef622adf3845edac3b0e0a1dcf6eb94bd /drivers/gpu/drm/radeon | |
parent | fa8198eac871edef38e969e2c6a68649e0cd36e0 (diff) |
drm/radeon/kms: add support for CP setup on cayman asics
Cayman asics have 3 ring buffers:
ring 0 supports both gfx and compute
rings 1 and 2 are compute only
At the moment we only support ring 0.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r-- | drivers/gpu/drm/radeon/Makefile | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/cayman_blit_shaders.c | 50 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/cayman_blit_shaders.h | 32 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 226 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/nid.h | 168 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 5 |
6 files changed, 482 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index e47eecfc2df4..230a53da09d3 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile | |||
@@ -66,7 +66,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ | |||
66 | r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ | 66 | r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ |
67 | r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ | 67 | r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ |
68 | evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ | 68 | evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ |
69 | radeon_trace_points.o ni.o | 69 | radeon_trace_points.o ni.o cayman_blit_shaders.o |
70 | 70 | ||
71 | radeon-$(CONFIG_COMPAT) += radeon_ioc32.o | 71 | radeon-$(CONFIG_COMPAT) += radeon_ioc32.o |
72 | radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o | 72 | radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o |
diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c new file mode 100644 index 000000000000..56be2b605d1f --- /dev/null +++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Advanced Micro Devices, Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice (including the next | ||
12 | * paragraph) shall be included in all copies or substantial portions of the | ||
13 | * Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
18 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
21 | * DEALINGS IN THE SOFTWARE. | ||
22 | * | ||
23 | * Authors: | ||
24 | * Alex Deucher <alexander.deucher@amd.com> | ||
25 | */ | ||
26 | |||
27 | #include <linux/types.h> | ||
28 | #include <linux/kernel.h> | ||
29 | |||
30 | /* | ||
31 | * evergreen cards need to use the 3D engine to blit data which requires | ||
32 | * quite a bit of hw state setup. Rather than pull the whole 3D driver | ||
33 | * (which normally generates the 3D state) into the DRM, we opt to use | ||
34 | * statically generated state tables. The regsiter state and shaders | ||
35 | * were hand generated to support blitting functionality. See the 3D | ||
36 | * driver or documentation for descriptions of the registers and | ||
37 | * shader instructions. | ||
38 | */ | ||
39 | |||
40 | const u32 cayman_default_state[] = | ||
41 | { | ||
42 | /* XXX fill in additional blit state */ | ||
43 | |||
44 | 0xc0026900, | ||
45 | 0x00000316, | ||
46 | 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | ||
47 | 0x00000010, /* */ | ||
48 | }; | ||
49 | |||
50 | const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state); | ||
diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.h b/drivers/gpu/drm/radeon/cayman_blit_shaders.h new file mode 100644 index 000000000000..33b75e5d0fa4 --- /dev/null +++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Advanced Micro Devices, Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice (including the next | ||
12 | * paragraph) shall be included in all copies or substantial portions of the | ||
13 | * Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
18 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
21 | * DEALINGS IN THE SOFTWARE. | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #ifndef CAYMAN_BLIT_SHADERS_H | ||
26 | #define CAYMAN_BLIT_SHADERS_H | ||
27 | |||
28 | extern const u32 cayman_default_state[]; | ||
29 | |||
30 | extern const u32 cayman_default_size; | ||
31 | |||
32 | #endif | ||
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 417d9c24fcdb..0fecad240007 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "nid.h" | 31 | #include "nid.h" |
32 | #include "atom.h" | 32 | #include "atom.h" |
33 | #include "ni_reg.h" | 33 | #include "ni_reg.h" |
34 | #include "cayman_blit_shaders.h" | ||
34 | 35 | ||
35 | #define EVERGREEN_PFP_UCODE_SIZE 1120 | 36 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
36 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | 37 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
@@ -1023,3 +1024,228 @@ void cayman_pcie_gart_fini(struct radeon_device *rdev) | |||
1023 | radeon_gart_fini(rdev); | 1024 | radeon_gart_fini(rdev); |
1024 | } | 1025 | } |
1025 | 1026 | ||
1027 | /* | ||
1028 | * CP. | ||
1029 | */ | ||
1030 | static void cayman_cp_enable(struct radeon_device *rdev, bool enable) | ||
1031 | { | ||
1032 | if (enable) | ||
1033 | WREG32(CP_ME_CNTL, 0); | ||
1034 | else { | ||
1035 | rdev->mc.active_vram_size = rdev->mc.visible_vram_size; | ||
1036 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); | ||
1037 | WREG32(SCRATCH_UMSK, 0); | ||
1038 | } | ||
1039 | } | ||
1040 | |||
1041 | static int cayman_cp_load_microcode(struct radeon_device *rdev) | ||
1042 | { | ||
1043 | const __be32 *fw_data; | ||
1044 | int i; | ||
1045 | |||
1046 | if (!rdev->me_fw || !rdev->pfp_fw) | ||
1047 | return -EINVAL; | ||
1048 | |||
1049 | cayman_cp_enable(rdev, false); | ||
1050 | |||
1051 | fw_data = (const __be32 *)rdev->pfp_fw->data; | ||
1052 | WREG32(CP_PFP_UCODE_ADDR, 0); | ||
1053 | for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++) | ||
1054 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); | ||
1055 | WREG32(CP_PFP_UCODE_ADDR, 0); | ||
1056 | |||
1057 | fw_data = (const __be32 *)rdev->me_fw->data; | ||
1058 | WREG32(CP_ME_RAM_WADDR, 0); | ||
1059 | for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++) | ||
1060 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); | ||
1061 | |||
1062 | WREG32(CP_PFP_UCODE_ADDR, 0); | ||
1063 | WREG32(CP_ME_RAM_WADDR, 0); | ||
1064 | WREG32(CP_ME_RAM_RADDR, 0); | ||
1065 | return 0; | ||
1066 | } | ||
1067 | |||
1068 | static int cayman_cp_start(struct radeon_device *rdev) | ||
1069 | { | ||
1070 | int r, i; | ||
1071 | |||
1072 | r = radeon_ring_lock(rdev, 7); | ||
1073 | if (r) { | ||
1074 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | ||
1075 | return r; | ||
1076 | } | ||
1077 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | ||
1078 | radeon_ring_write(rdev, 0x1); | ||
1079 | radeon_ring_write(rdev, 0x0); | ||
1080 | radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1); | ||
1081 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | ||
1082 | radeon_ring_write(rdev, 0); | ||
1083 | radeon_ring_write(rdev, 0); | ||
1084 | radeon_ring_unlock_commit(rdev); | ||
1085 | |||
1086 | cayman_cp_enable(rdev, true); | ||
1087 | |||
1088 | r = radeon_ring_lock(rdev, cayman_default_size + 15); | ||
1089 | if (r) { | ||
1090 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | ||
1091 | return r; | ||
1092 | } | ||
1093 | |||
1094 | /* setup clear context state */ | ||
1095 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | ||
1096 | radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); | ||
1097 | |||
1098 | for (i = 0; i < cayman_default_size; i++) | ||
1099 | radeon_ring_write(rdev, cayman_default_state[i]); | ||
1100 | |||
1101 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | ||
1102 | radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); | ||
1103 | |||
1104 | /* set clear context state */ | ||
1105 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); | ||
1106 | radeon_ring_write(rdev, 0); | ||
1107 | |||
1108 | /* SQ_VTX_BASE_VTX_LOC */ | ||
1109 | radeon_ring_write(rdev, 0xc0026f00); | ||
1110 | radeon_ring_write(rdev, 0x00000000); | ||
1111 | radeon_ring_write(rdev, 0x00000000); | ||
1112 | radeon_ring_write(rdev, 0x00000000); | ||
1113 | |||
1114 | /* Clear consts */ | ||
1115 | radeon_ring_write(rdev, 0xc0036f00); | ||
1116 | radeon_ring_write(rdev, 0x00000bc4); | ||
1117 | radeon_ring_write(rdev, 0xffffffff); | ||
1118 | radeon_ring_write(rdev, 0xffffffff); | ||
1119 | radeon_ring_write(rdev, 0xffffffff); | ||
1120 | |||
1121 | radeon_ring_unlock_commit(rdev); | ||
1122 | |||
1123 | /* XXX init other rings */ | ||
1124 | |||
1125 | return 0; | ||
1126 | } | ||
1127 | |||
1128 | int cayman_cp_resume(struct radeon_device *rdev) | ||
1129 | { | ||
1130 | u32 tmp; | ||
1131 | u32 rb_bufsz; | ||
1132 | int r; | ||
1133 | |||
1134 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ | ||
1135 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | | ||
1136 | SOFT_RESET_PA | | ||
1137 | SOFT_RESET_SH | | ||
1138 | SOFT_RESET_VGT | | ||
1139 | SOFT_RESET_SX)); | ||
1140 | RREG32(GRBM_SOFT_RESET); | ||
1141 | mdelay(15); | ||
1142 | WREG32(GRBM_SOFT_RESET, 0); | ||
1143 | RREG32(GRBM_SOFT_RESET); | ||
1144 | |||
1145 | WREG32(CP_SEM_WAIT_TIMER, 0x4); | ||
1146 | |||
1147 | /* Set the write pointer delay */ | ||
1148 | WREG32(CP_RB_WPTR_DELAY, 0); | ||
1149 | |||
1150 | WREG32(CP_DEBUG, (1 << 27)); | ||
1151 | |||
1152 | /* ring 0 - compute and gfx */ | ||
1153 | /* Set ring buffer size */ | ||
1154 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); | ||
1155 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | ||
1156 | #ifdef __BIG_ENDIAN | ||
1157 | tmp |= BUF_SWAP_32BIT; | ||
1158 | #endif | ||
1159 | WREG32(CP_RB0_CNTL, tmp); | ||
1160 | |||
1161 | /* Initialize the ring buffer's read and write pointers */ | ||
1162 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); | ||
1163 | WREG32(CP_RB0_WPTR, 0); | ||
1164 | |||
1165 | /* set the wb address wether it's enabled or not */ | ||
1166 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | ||
1167 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); | ||
1168 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | ||
1169 | |||
1170 | if (rdev->wb.enabled) | ||
1171 | WREG32(SCRATCH_UMSK, 0xff); | ||
1172 | else { | ||
1173 | tmp |= RB_NO_UPDATE; | ||
1174 | WREG32(SCRATCH_UMSK, 0); | ||
1175 | } | ||
1176 | |||
1177 | mdelay(1); | ||
1178 | WREG32(CP_RB0_CNTL, tmp); | ||
1179 | |||
1180 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); | ||
1181 | |||
1182 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); | ||
1183 | rdev->cp.wptr = RREG32(CP_RB0_WPTR); | ||
1184 | |||
1185 | /* ring1 - compute only */ | ||
1186 | /* Set ring buffer size */ | ||
1187 | rb_bufsz = drm_order(rdev->cp1.ring_size / 8); | ||
1188 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | ||
1189 | #ifdef __BIG_ENDIAN | ||
1190 | tmp |= BUF_SWAP_32BIT; | ||
1191 | #endif | ||
1192 | WREG32(CP_RB1_CNTL, tmp); | ||
1193 | |||
1194 | /* Initialize the ring buffer's read and write pointers */ | ||
1195 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); | ||
1196 | WREG32(CP_RB1_WPTR, 0); | ||
1197 | |||
1198 | /* set the wb address wether it's enabled or not */ | ||
1199 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); | ||
1200 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); | ||
1201 | |||
1202 | mdelay(1); | ||
1203 | WREG32(CP_RB1_CNTL, tmp); | ||
1204 | |||
1205 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); | ||
1206 | |||
1207 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); | ||
1208 | rdev->cp1.wptr = RREG32(CP_RB1_WPTR); | ||
1209 | |||
1210 | /* ring2 - compute only */ | ||
1211 | /* Set ring buffer size */ | ||
1212 | rb_bufsz = drm_order(rdev->cp2.ring_size / 8); | ||
1213 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | ||
1214 | #ifdef __BIG_ENDIAN | ||
1215 | tmp |= BUF_SWAP_32BIT; | ||
1216 | #endif | ||
1217 | WREG32(CP_RB2_CNTL, tmp); | ||
1218 | |||
1219 | /* Initialize the ring buffer's read and write pointers */ | ||
1220 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); | ||
1221 | WREG32(CP_RB2_WPTR, 0); | ||
1222 | |||
1223 | /* set the wb address wether it's enabled or not */ | ||
1224 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); | ||
1225 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); | ||
1226 | |||
1227 | mdelay(1); | ||
1228 | WREG32(CP_RB2_CNTL, tmp); | ||
1229 | |||
1230 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); | ||
1231 | |||
1232 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); | ||
1233 | rdev->cp2.wptr = RREG32(CP_RB2_WPTR); | ||
1234 | |||
1235 | /* start the rings */ | ||
1236 | cayman_cp_start(rdev); | ||
1237 | rdev->cp.ready = true; | ||
1238 | rdev->cp1.ready = true; | ||
1239 | rdev->cp2.ready = true; | ||
1240 | /* this only test cp0 */ | ||
1241 | r = radeon_ring_test(rdev); | ||
1242 | if (r) { | ||
1243 | rdev->cp.ready = false; | ||
1244 | rdev->cp1.ready = false; | ||
1245 | rdev->cp2.ready = false; | ||
1246 | return r; | ||
1247 | } | ||
1248 | |||
1249 | return 0; | ||
1250 | } | ||
1251 | |||
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h index 9dc2b3429c3f..57062f14acc9 100644 --- a/drivers/gpu/drm/radeon/nid.h +++ b/drivers/gpu/drm/radeon/nid.h | |||
@@ -205,6 +205,24 @@ | |||
205 | #define SOFT_RESET_VGT (1 << 14) | 205 | #define SOFT_RESET_VGT (1 << 14) |
206 | #define SOFT_RESET_IA (1 << 15) | 206 | #define SOFT_RESET_IA (1 << 15) |
207 | 207 | ||
208 | #define SCRATCH_REG0 0x8500 | ||
209 | #define SCRATCH_REG1 0x8504 | ||
210 | #define SCRATCH_REG2 0x8508 | ||
211 | #define SCRATCH_REG3 0x850C | ||
212 | #define SCRATCH_REG4 0x8510 | ||
213 | #define SCRATCH_REG5 0x8514 | ||
214 | #define SCRATCH_REG6 0x8518 | ||
215 | #define SCRATCH_REG7 0x851C | ||
216 | #define SCRATCH_UMSK 0x8540 | ||
217 | #define SCRATCH_ADDR 0x8544 | ||
218 | #define CP_SEM_WAIT_TIMER 0x85BC | ||
219 | #define CP_ME_CNTL 0x86D8 | ||
220 | #define CP_ME_HALT (1 << 28) | ||
221 | #define CP_PFP_HALT (1 << 26) | ||
222 | #define CP_RB2_RPTR 0x86f8 | ||
223 | #define CP_RB1_RPTR 0x86fc | ||
224 | #define CP_RB0_RPTR 0x8700 | ||
225 | #define CP_RB_WPTR_DELAY 0x8704 | ||
208 | #define CP_MEQ_THRESHOLDS 0x8764 | 226 | #define CP_MEQ_THRESHOLDS 0x8764 |
209 | #define MEQ1_START(x) ((x) << 0) | 227 | #define MEQ1_START(x) ((x) << 0) |
210 | #define MEQ2_START(x) ((x) << 8) | 228 | #define MEQ2_START(x) ((x) << 8) |
@@ -363,5 +381,155 @@ | |||
363 | #define ACK_FLUSH_CTL(x) ((x) << 6) | 381 | #define ACK_FLUSH_CTL(x) ((x) << 6) |
364 | #define SYNC_FLUSH_CTL (1 << 8) | 382 | #define SYNC_FLUSH_CTL (1 << 8) |
365 | 383 | ||
384 | #define CP_RB0_BASE 0xC100 | ||
385 | #define CP_RB0_CNTL 0xC104 | ||
386 | #define RB_BUFSZ(x) ((x) << 0) | ||
387 | #define RB_BLKSZ(x) ((x) << 8) | ||
388 | #define RB_NO_UPDATE (1 << 27) | ||
389 | #define RB_RPTR_WR_ENA (1 << 31) | ||
390 | #define BUF_SWAP_32BIT (2 << 16) | ||
391 | #define CP_RB0_RPTR_ADDR 0xC10C | ||
392 | #define CP_RB0_RPTR_ADDR_HI 0xC110 | ||
393 | #define CP_RB0_WPTR 0xC114 | ||
394 | #define CP_RB1_BASE 0xC180 | ||
395 | #define CP_RB1_CNTL 0xC184 | ||
396 | #define CP_RB1_RPTR_ADDR 0xC188 | ||
397 | #define CP_RB1_RPTR_ADDR_HI 0xC18C | ||
398 | #define CP_RB1_WPTR 0xC190 | ||
399 | #define CP_RB2_BASE 0xC194 | ||
400 | #define CP_RB2_CNTL 0xC198 | ||
401 | #define CP_RB2_RPTR_ADDR 0xC19C | ||
402 | #define CP_RB2_RPTR_ADDR_HI 0xC1A0 | ||
403 | #define CP_RB2_WPTR 0xC1A4 | ||
404 | #define CP_PFP_UCODE_ADDR 0xC150 | ||
405 | #define CP_PFP_UCODE_DATA 0xC154 | ||
406 | #define CP_ME_RAM_RADDR 0xC158 | ||
407 | #define CP_ME_RAM_WADDR 0xC15C | ||
408 | #define CP_ME_RAM_DATA 0xC160 | ||
409 | #define CP_DEBUG 0xC1FC | ||
410 | |||
411 | /* | ||
412 | * PM4 | ||
413 | */ | ||
414 | #define PACKET_TYPE0 0 | ||
415 | #define PACKET_TYPE1 1 | ||
416 | #define PACKET_TYPE2 2 | ||
417 | #define PACKET_TYPE3 3 | ||
418 | |||
419 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) | ||
420 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) | ||
421 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) | ||
422 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | ||
423 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ | ||
424 | (((reg) >> 2) & 0xFFFF) | \ | ||
425 | ((n) & 0x3FFF) << 16) | ||
426 | #define CP_PACKET2 0x80000000 | ||
427 | #define PACKET2_PAD_SHIFT 0 | ||
428 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | ||
429 | |||
430 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | ||
431 | |||
432 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ | ||
433 | (((op) & 0xFF) << 8) | \ | ||
434 | ((n) & 0x3FFF) << 16) | ||
435 | |||
436 | /* Packet 3 types */ | ||
437 | #define PACKET3_NOP 0x10 | ||
438 | #define PACKET3_SET_BASE 0x11 | ||
439 | #define PACKET3_CLEAR_STATE 0x12 | ||
440 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 | ||
441 | #define PACKET3_DEALLOC_STATE 0x14 | ||
442 | #define PACKET3_DISPATCH_DIRECT 0x15 | ||
443 | #define PACKET3_DISPATCH_INDIRECT 0x16 | ||
444 | #define PACKET3_INDIRECT_BUFFER_END 0x17 | ||
445 | #define PACKET3_SET_PREDICATION 0x20 | ||
446 | #define PACKET3_REG_RMW 0x21 | ||
447 | #define PACKET3_COND_EXEC 0x22 | ||
448 | #define PACKET3_PRED_EXEC 0x23 | ||
449 | #define PACKET3_DRAW_INDIRECT 0x24 | ||
450 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 | ||
451 | #define PACKET3_INDEX_BASE 0x26 | ||
452 | #define PACKET3_DRAW_INDEX_2 0x27 | ||
453 | #define PACKET3_CONTEXT_CONTROL 0x28 | ||
454 | #define PACKET3_DRAW_INDEX_OFFSET 0x29 | ||
455 | #define PACKET3_INDEX_TYPE 0x2A | ||
456 | #define PACKET3_DRAW_INDEX 0x2B | ||
457 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | ||
458 | #define PACKET3_DRAW_INDEX_IMMD 0x2E | ||
459 | #define PACKET3_NUM_INSTANCES 0x2F | ||
460 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 | ||
461 | #define PACKET3_INDIRECT_BUFFER 0x32 | ||
462 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | ||
463 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 | ||
464 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 | ||
465 | #define PACKET3_WRITE_DATA 0x37 | ||
466 | #define PACKET3_MEM_SEMAPHORE 0x39 | ||
467 | #define PACKET3_MPEG_INDEX 0x3A | ||
468 | #define PACKET3_WAIT_REG_MEM 0x3C | ||
469 | #define PACKET3_MEM_WRITE 0x3D | ||
470 | #define PACKET3_SURFACE_SYNC 0x43 | ||
471 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | ||
472 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) | ||
473 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) | ||
474 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) | ||
475 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) | ||
476 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) | ||
477 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) | ||
478 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) | ||
479 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) | ||
480 | # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) | ||
481 | # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) | ||
482 | # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) | ||
483 | # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) | ||
484 | # define PACKET3_FULL_CACHE_ENA (1 << 20) | ||
485 | # define PACKET3_TC_ACTION_ENA (1 << 23) | ||
486 | # define PACKET3_CB_ACTION_ENA (1 << 25) | ||
487 | # define PACKET3_DB_ACTION_ENA (1 << 26) | ||
488 | # define PACKET3_SH_ACTION_ENA (1 << 27) | ||
489 | # define PACKET3_SX_ACTION_ENA (1 << 28) | ||
490 | #define PACKET3_ME_INITIALIZE 0x44 | ||
491 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) | ||
492 | #define PACKET3_COND_WRITE 0x45 | ||
493 | #define PACKET3_EVENT_WRITE 0x46 | ||
494 | #define PACKET3_EVENT_WRITE_EOP 0x47 | ||
495 | #define PACKET3_EVENT_WRITE_EOS 0x48 | ||
496 | #define PACKET3_PREAMBLE_CNTL 0x4A | ||
497 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) | ||
498 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) | ||
499 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C | ||
500 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D | ||
501 | #define PACKET3_ALU_PS_CONST_UPDATE 0x4E | ||
502 | #define PACKET3_ALU_VS_CONST_UPDATE 0x4F | ||
503 | #define PACKET3_ONE_REG_WRITE 0x57 | ||
504 | #define PACKET3_SET_CONFIG_REG 0x68 | ||
505 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 | ||
506 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 | ||
507 | #define PACKET3_SET_CONTEXT_REG 0x69 | ||
508 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 | ||
509 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 | ||
510 | #define PACKET3_SET_ALU_CONST 0x6A | ||
511 | /* alu const buffers only; no reg file */ | ||
512 | #define PACKET3_SET_BOOL_CONST 0x6B | ||
513 | #define PACKET3_SET_BOOL_CONST_START 0x0003a500 | ||
514 | #define PACKET3_SET_BOOL_CONST_END 0x0003a518 | ||
515 | #define PACKET3_SET_LOOP_CONST 0x6C | ||
516 | #define PACKET3_SET_LOOP_CONST_START 0x0003a200 | ||
517 | #define PACKET3_SET_LOOP_CONST_END 0x0003a500 | ||
518 | #define PACKET3_SET_RESOURCE 0x6D | ||
519 | #define PACKET3_SET_RESOURCE_START 0x00030000 | ||
520 | #define PACKET3_SET_RESOURCE_END 0x00038000 | ||
521 | #define PACKET3_SET_SAMPLER 0x6E | ||
522 | #define PACKET3_SET_SAMPLER_START 0x0003c000 | ||
523 | #define PACKET3_SET_SAMPLER_END 0x0003c600 | ||
524 | #define PACKET3_SET_CTL_CONST 0x6F | ||
525 | #define PACKET3_SET_CTL_CONST_START 0x0003cff0 | ||
526 | #define PACKET3_SET_CTL_CONST_END 0x0003ff0c | ||
527 | #define PACKET3_SET_RESOURCE_OFFSET 0x70 | ||
528 | #define PACKET3_SET_ALU_CONST_VS 0x71 | ||
529 | #define PACKET3_SET_ALU_CONST_DI 0x72 | ||
530 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 | ||
531 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 | ||
532 | #define PACKET3_SET_APPEND_CNT 0x75 | ||
533 | |||
366 | #endif | 534 | #endif |
367 | 535 | ||
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 4b77b79fbbc2..4ff28d68a498 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -664,6 +664,8 @@ struct radeon_wb { | |||
664 | 664 | ||
665 | #define RADEON_WB_SCRATCH_OFFSET 0 | 665 | #define RADEON_WB_SCRATCH_OFFSET 0 |
666 | #define RADEON_WB_CP_RPTR_OFFSET 1024 | 666 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
667 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 | ||
668 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | ||
667 | #define R600_WB_IH_WPTR_OFFSET 2048 | 669 | #define R600_WB_IH_WPTR_OFFSET 2048 |
668 | #define R600_WB_EVENT_OFFSET 3072 | 670 | #define R600_WB_EVENT_OFFSET 3072 |
669 | 671 | ||
@@ -1186,6 +1188,9 @@ struct radeon_device { | |||
1186 | struct radeon_mman mman; | 1188 | struct radeon_mman mman; |
1187 | struct radeon_fence_driver fence_drv; | 1189 | struct radeon_fence_driver fence_drv; |
1188 | struct radeon_cp cp; | 1190 | struct radeon_cp cp; |
1191 | /* cayman compute rings */ | ||
1192 | struct radeon_cp cp1; | ||
1193 | struct radeon_cp cp2; | ||
1189 | struct radeon_ib_pool ib_pool; | 1194 | struct radeon_ib_pool ib_pool; |
1190 | struct radeon_irq irq; | 1195 | struct radeon_irq irq; |
1191 | struct radeon_asic *asic; | 1196 | struct radeon_asic *asic; |