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authorAlex Deucher <alexander.deucher@amd.com>2012-11-07 20:05:07 -0500
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 19:15:48 -0400
commit0c4aaeae441495b21b9c7d306098ee4911bfa16a (patch)
tree6865baac28f703c024262ba1feb0ef8b63d57c69 /drivers/gpu/drm/radeon/trinity_dpm.h
parent06793dfba2215f3d31a7a12e5fd8901f18ee035a (diff)
drm/radeon: add dpm UVD handling for TN asics (v2)
v2: fix typo noticed by Dan Carpenter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/trinity_dpm.h')
-rw-r--r--drivers/gpu/drm/radeon/trinity_dpm.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.h b/drivers/gpu/drm/radeon/trinity_dpm.h
index 15e050fd5446..31100ac64245 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.h
+++ b/drivers/gpu/drm/radeon/trinity_dpm.h
@@ -55,14 +55,29 @@ struct trinity_ps {
55 u8 Dpm0PgNbPsHi; 55 u8 Dpm0PgNbPsHi;
56 u8 DpmXNbPsLo; 56 u8 DpmXNbPsLo;
57 u8 DpmXNbPsHi; 57 u8 DpmXNbPsHi;
58
59 u32 vclk_low_divider;
60 u32 vclk_high_divider;
61 u32 dclk_low_divider;
62 u32 dclk_high_divider;
58}; 63};
59 64
60#define TRINITY_NUM_NBPSTATES 4 65#define TRINITY_NUM_NBPSTATES 4
61 66
67struct trinity_uvd_clock_table_entry
68{
69 u32 vclk;
70 u32 dclk;
71 u8 vclk_did;
72 u8 dclk_did;
73 u8 rsv[2];
74};
75
62struct trinity_sys_info { 76struct trinity_sys_info {
63 u32 bootup_uma_clk; 77 u32 bootup_uma_clk;
64 u32 bootup_sclk; 78 u32 bootup_sclk;
65 u32 min_sclk; 79 u32 min_sclk;
80 u32 dentist_vco_freq;
66 u32 nb_dpm_enable; 81 u32 nb_dpm_enable;
67 u32 nbp_mclk[TRINITY_NUM_NBPSTATES]; 82 u32 nbp_mclk[TRINITY_NUM_NBPSTATES];
68 u32 nbp_nclk[TRINITY_NUM_NBPSTATES]; 83 u32 nbp_nclk[TRINITY_NUM_NBPSTATES];
@@ -73,6 +88,7 @@ struct trinity_sys_info {
73 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 88 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
74 struct sumo_vid_mapping_table vid_mapping_table; 89 struct sumo_vid_mapping_table vid_mapping_table;
75 u32 uma_channel_number; 90 u32 uma_channel_number;
91 struct trinity_uvd_clock_table_entry uvd_clock_table_entries[4];
76}; 92};
77 93
78struct trinity_power_info { 94struct trinity_power_info {
@@ -93,12 +109,14 @@ struct trinity_power_info {
93 bool enable_auto_thermal_throttling; 109 bool enable_auto_thermal_throttling;
94 bool enable_dpm; 110 bool enable_dpm;
95 bool enable_sclk_ds; 111 bool enable_sclk_ds;
112 bool uvd_dpm;
96}; 113};
97 114
98#define TRINITY_AT_DFLT 30 115#define TRINITY_AT_DFLT 30
99 116
100/* trinity_smc.c */ 117/* trinity_smc.c */
101int trinity_dpm_config(struct radeon_device *rdev, bool enable); 118int trinity_dpm_config(struct radeon_device *rdev, bool enable);
119int trinity_uvd_dpm_config(struct radeon_device *rdev);
102int trinity_dpm_force_state(struct radeon_device *rdev, u32 n); 120int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);
103int trinity_dpm_no_forced_level(struct radeon_device *rdev); 121int trinity_dpm_no_forced_level(struct radeon_device *rdev);
104int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev, 122int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev,