diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-10-07 10:43:04 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-10-07 10:43:04 -0400 |
commit | a56e74f546b64be93731e42d83baf5b538cc1b11 (patch) | |
tree | 18f6dee45d801e57ac9db2a31664b0d5c0762c50 /drivers/gpu/drm/radeon/si_smc.c | |
parent | d08e2e09042bd3f7ef66a35cb4bb92794ab26bb2 (diff) | |
parent | e4e7f10bfc4069925e99cc4b428c3434e30b6c3f (diff) |
Merge branch 'arm-aesbs' of git://git.linaro.org/people/ardbiesheuvel/linux-arm into devel-stable
Diffstat (limited to 'drivers/gpu/drm/radeon/si_smc.c')
-rw-r--r-- | drivers/gpu/drm/radeon/si_smc.c | 43 |
1 files changed, 28 insertions, 15 deletions
diff --git a/drivers/gpu/drm/radeon/si_smc.c b/drivers/gpu/drm/radeon/si_smc.c index 5f524c0a541e..d422a1cbf727 100644 --- a/drivers/gpu/drm/radeon/si_smc.c +++ b/drivers/gpu/drm/radeon/si_smc.c | |||
@@ -29,8 +29,8 @@ | |||
29 | #include "ppsmc.h" | 29 | #include "ppsmc.h" |
30 | #include "radeon_ucode.h" | 30 | #include "radeon_ucode.h" |
31 | 31 | ||
32 | int si_set_smc_sram_address(struct radeon_device *rdev, | 32 | static int si_set_smc_sram_address(struct radeon_device *rdev, |
33 | u32 smc_address, u32 limit) | 33 | u32 smc_address, u32 limit) |
34 | { | 34 | { |
35 | if (smc_address & 3) | 35 | if (smc_address & 3) |
36 | return -EINVAL; | 36 | return -EINVAL; |
@@ -47,7 +47,8 @@ int si_copy_bytes_to_smc(struct radeon_device *rdev, | |||
47 | u32 smc_start_address, | 47 | u32 smc_start_address, |
48 | const u8 *src, u32 byte_count, u32 limit) | 48 | const u8 *src, u32 byte_count, u32 limit) |
49 | { | 49 | { |
50 | int ret; | 50 | unsigned long flags; |
51 | int ret = 0; | ||
51 | u32 data, original_data, addr, extra_shift; | 52 | u32 data, original_data, addr, extra_shift; |
52 | 53 | ||
53 | if (smc_start_address & 3) | 54 | if (smc_start_address & 3) |
@@ -57,13 +58,14 @@ int si_copy_bytes_to_smc(struct radeon_device *rdev, | |||
57 | 58 | ||
58 | addr = smc_start_address; | 59 | addr = smc_start_address; |
59 | 60 | ||
61 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | ||
60 | while (byte_count >= 4) { | 62 | while (byte_count >= 4) { |
61 | /* SMC address space is BE */ | 63 | /* SMC address space is BE */ |
62 | data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; | 64 | data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; |
63 | 65 | ||
64 | ret = si_set_smc_sram_address(rdev, addr, limit); | 66 | ret = si_set_smc_sram_address(rdev, addr, limit); |
65 | if (ret) | 67 | if (ret) |
66 | return ret; | 68 | goto done; |
67 | 69 | ||
68 | WREG32(SMC_IND_DATA_0, data); | 70 | WREG32(SMC_IND_DATA_0, data); |
69 | 71 | ||
@@ -78,7 +80,7 @@ int si_copy_bytes_to_smc(struct radeon_device *rdev, | |||
78 | 80 | ||
79 | ret = si_set_smc_sram_address(rdev, addr, limit); | 81 | ret = si_set_smc_sram_address(rdev, addr, limit); |
80 | if (ret) | 82 | if (ret) |
81 | return ret; | 83 | goto done; |
82 | 84 | ||
83 | original_data = RREG32(SMC_IND_DATA_0); | 85 | original_data = RREG32(SMC_IND_DATA_0); |
84 | 86 | ||
@@ -96,11 +98,15 @@ int si_copy_bytes_to_smc(struct radeon_device *rdev, | |||
96 | 98 | ||
97 | ret = si_set_smc_sram_address(rdev, addr, limit); | 99 | ret = si_set_smc_sram_address(rdev, addr, limit); |
98 | if (ret) | 100 | if (ret) |
99 | return ret; | 101 | goto done; |
100 | 102 | ||
101 | WREG32(SMC_IND_DATA_0, data); | 103 | WREG32(SMC_IND_DATA_0, data); |
102 | } | 104 | } |
103 | return 0; | 105 | |
106 | done: | ||
107 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); | ||
108 | |||
109 | return ret; | ||
104 | } | 110 | } |
105 | 111 | ||
106 | void si_start_smc(struct radeon_device *rdev) | 112 | void si_start_smc(struct radeon_device *rdev) |
@@ -203,6 +209,7 @@ PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev) | |||
203 | 209 | ||
204 | int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) | 210 | int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) |
205 | { | 211 | { |
212 | unsigned long flags; | ||
206 | u32 ucode_start_address; | 213 | u32 ucode_start_address; |
207 | u32 ucode_size; | 214 | u32 ucode_size; |
208 | const u8 *src; | 215 | const u8 *src; |
@@ -241,6 +248,7 @@ int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) | |||
241 | return -EINVAL; | 248 | return -EINVAL; |
242 | 249 | ||
243 | src = (const u8 *)rdev->smc_fw->data; | 250 | src = (const u8 *)rdev->smc_fw->data; |
251 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | ||
244 | WREG32(SMC_IND_INDEX_0, ucode_start_address); | 252 | WREG32(SMC_IND_INDEX_0, ucode_start_address); |
245 | WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); | 253 | WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); |
246 | while (ucode_size >= 4) { | 254 | while (ucode_size >= 4) { |
@@ -253,6 +261,7 @@ int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) | |||
253 | ucode_size -= 4; | 261 | ucode_size -= 4; |
254 | } | 262 | } |
255 | WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); | 263 | WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); |
264 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); | ||
256 | 265 | ||
257 | return 0; | 266 | return 0; |
258 | } | 267 | } |
@@ -260,25 +269,29 @@ int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) | |||
260 | int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, | 269 | int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, |
261 | u32 *value, u32 limit) | 270 | u32 *value, u32 limit) |
262 | { | 271 | { |
272 | unsigned long flags; | ||
263 | int ret; | 273 | int ret; |
264 | 274 | ||
275 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | ||
265 | ret = si_set_smc_sram_address(rdev, smc_address, limit); | 276 | ret = si_set_smc_sram_address(rdev, smc_address, limit); |
266 | if (ret) | 277 | if (ret == 0) |
267 | return ret; | 278 | *value = RREG32(SMC_IND_DATA_0); |
279 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); | ||
268 | 280 | ||
269 | *value = RREG32(SMC_IND_DATA_0); | 281 | return ret; |
270 | return 0; | ||
271 | } | 282 | } |
272 | 283 | ||
273 | int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, | 284 | int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, |
274 | u32 value, u32 limit) | 285 | u32 value, u32 limit) |
275 | { | 286 | { |
287 | unsigned long flags; | ||
276 | int ret; | 288 | int ret; |
277 | 289 | ||
290 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | ||
278 | ret = si_set_smc_sram_address(rdev, smc_address, limit); | 291 | ret = si_set_smc_sram_address(rdev, smc_address, limit); |
279 | if (ret) | 292 | if (ret == 0) |
280 | return ret; | 293 | WREG32(SMC_IND_DATA_0, value); |
294 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); | ||
281 | 295 | ||
282 | WREG32(SMC_IND_DATA_0, value); | 296 | return ret; |
283 | return 0; | ||
284 | } | 297 | } |