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author | Alex Deucher <alexander.deucher@amd.com> | 2013-07-26 18:05:07 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2013-07-29 18:14:36 -0400 |
commit | 489bc476b4c2b3097fe9e980379bbbab260a6156 (patch) | |
tree | 6e269f9c0144433d8d9a955173f90d65e9f9153a /drivers/gpu/drm/radeon/si_dpm.c | |
parent | 7d61d835824f73dc4097b51f800382467c8049c5 (diff) |
drm/radeon/dpm: fix display gap programming on SI
Need to set the DISP*_GAP fields as well as the
DISP*_GAP_MCHG fields. Same as on previous asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si_dpm.c')
-rw-r--r-- | drivers/gpu/drm/radeon/si_dpm.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 73aaa2e4c312..6ecbb875d211 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c | |||
@@ -3620,8 +3620,12 @@ static void si_enable_display_gap(struct radeon_device *rdev) | |||
3620 | { | 3620 | { |
3621 | u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); | 3621 | u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); |
3622 | 3622 | ||
3623 | tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); | ||
3624 | tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | | ||
3625 | DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); | ||
3626 | |||
3623 | tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); | 3627 | tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); |
3624 | tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) | | 3628 | tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | |
3625 | DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); | 3629 | DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); |
3626 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); | 3630 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); |
3627 | } | 3631 | } |