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authorAlex Deucher <alexander.deucher@amd.com>2013-06-13 18:47:58 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-07-14 10:11:29 -0400
commitfbf6dc7ac7291841f53367d461a01a8e8bad0369 (patch)
tree43153f9c70b7ada6e274819d5b12403ac14f79eb /drivers/gpu/drm/radeon/si.c
parent54e2e49ce28ff7ac67b93e7e9e44702552b04a69 (diff)
drm/radeon: add fault decode function for SI (v2)
Helpful for debugging GPUVM errors as we can see what hw block and page generated the fault in the log. v2: simplify fault decoding Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c272
1 files changed, 270 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index f305768c3dfa..d3f05076f385 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4390,6 +4390,270 @@ void si_vm_fini(struct radeon_device *rdev)
4390} 4390}
4391 4391
4392/** 4392/**
4393 * si_vm_decode_fault - print human readable fault info
4394 *
4395 * @rdev: radeon_device pointer
4396 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
4397 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
4398 *
4399 * Print human readable fault information (SI).
4400 */
4401static void si_vm_decode_fault(struct radeon_device *rdev,
4402 u32 status, u32 addr)
4403{
4404 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
4405 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4406 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4407 char *block;
4408
4409 if (rdev->family == CHIP_TAHITI) {
4410 switch (mc_id) {
4411 case 160:
4412 case 144:
4413 case 96:
4414 case 80:
4415 case 224:
4416 case 208:
4417 case 32:
4418 case 16:
4419 block = "CB";
4420 break;
4421 case 161:
4422 case 145:
4423 case 97:
4424 case 81:
4425 case 225:
4426 case 209:
4427 case 33:
4428 case 17:
4429 block = "CB_FMASK";
4430 break;
4431 case 162:
4432 case 146:
4433 case 98:
4434 case 82:
4435 case 226:
4436 case 210:
4437 case 34:
4438 case 18:
4439 block = "CB_CMASK";
4440 break;
4441 case 163:
4442 case 147:
4443 case 99:
4444 case 83:
4445 case 227:
4446 case 211:
4447 case 35:
4448 case 19:
4449 block = "CB_IMMED";
4450 break;
4451 case 164:
4452 case 148:
4453 case 100:
4454 case 84:
4455 case 228:
4456 case 212:
4457 case 36:
4458 case 20:
4459 block = "DB";
4460 break;
4461 case 165:
4462 case 149:
4463 case 101:
4464 case 85:
4465 case 229:
4466 case 213:
4467 case 37:
4468 case 21:
4469 block = "DB_HTILE";
4470 break;
4471 case 167:
4472 case 151:
4473 case 103:
4474 case 87:
4475 case 231:
4476 case 215:
4477 case 39:
4478 case 23:
4479 block = "DB_STEN";
4480 break;
4481 case 72:
4482 case 68:
4483 case 64:
4484 case 8:
4485 case 4:
4486 case 0:
4487 case 136:
4488 case 132:
4489 case 128:
4490 case 200:
4491 case 196:
4492 case 192:
4493 block = "TC";
4494 break;
4495 case 112:
4496 case 48:
4497 block = "CP";
4498 break;
4499 case 49:
4500 case 177:
4501 case 50:
4502 case 178:
4503 block = "SH";
4504 break;
4505 case 53:
4506 case 190:
4507 block = "VGT";
4508 break;
4509 case 117:
4510 block = "IH";
4511 break;
4512 case 51:
4513 case 115:
4514 block = "RLC";
4515 break;
4516 case 119:
4517 case 183:
4518 block = "DMA0";
4519 break;
4520 case 61:
4521 block = "DMA1";
4522 break;
4523 case 248:
4524 case 120:
4525 block = "HDP";
4526 break;
4527 default:
4528 block = "unknown";
4529 break;
4530 }
4531 } else {
4532 switch (mc_id) {
4533 case 32:
4534 case 16:
4535 case 96:
4536 case 80:
4537 case 160:
4538 case 144:
4539 case 224:
4540 case 208:
4541 block = "CB";
4542 break;
4543 case 33:
4544 case 17:
4545 case 97:
4546 case 81:
4547 case 161:
4548 case 145:
4549 case 225:
4550 case 209:
4551 block = "CB_FMASK";
4552 break;
4553 case 34:
4554 case 18:
4555 case 98:
4556 case 82:
4557 case 162:
4558 case 146:
4559 case 226:
4560 case 210:
4561 block = "CB_CMASK";
4562 break;
4563 case 35:
4564 case 19:
4565 case 99:
4566 case 83:
4567 case 163:
4568 case 147:
4569 case 227:
4570 case 211:
4571 block = "CB_IMMED";
4572 break;
4573 case 36:
4574 case 20:
4575 case 100:
4576 case 84:
4577 case 164:
4578 case 148:
4579 case 228:
4580 case 212:
4581 block = "DB";
4582 break;
4583 case 37:
4584 case 21:
4585 case 101:
4586 case 85:
4587 case 165:
4588 case 149:
4589 case 229:
4590 case 213:
4591 block = "DB_HTILE";
4592 break;
4593 case 39:
4594 case 23:
4595 case 103:
4596 case 87:
4597 case 167:
4598 case 151:
4599 case 231:
4600 case 215:
4601 block = "DB_STEN";
4602 break;
4603 case 72:
4604 case 68:
4605 case 8:
4606 case 4:
4607 case 136:
4608 case 132:
4609 case 200:
4610 case 196:
4611 block = "TC";
4612 break;
4613 case 112:
4614 case 48:
4615 block = "CP";
4616 break;
4617 case 49:
4618 case 177:
4619 case 50:
4620 case 178:
4621 block = "SH";
4622 break;
4623 case 53:
4624 block = "VGT";
4625 break;
4626 case 117:
4627 block = "IH";
4628 break;
4629 case 51:
4630 case 115:
4631 block = "RLC";
4632 break;
4633 case 119:
4634 case 183:
4635 block = "DMA0";
4636 break;
4637 case 61:
4638 block = "DMA1";
4639 break;
4640 case 248:
4641 case 120:
4642 block = "HDP";
4643 break;
4644 default:
4645 block = "unknown";
4646 break;
4647 }
4648 }
4649
4650 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
4651 protections, vmid, addr,
4652 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
4653 block, mc_id);
4654}
4655
4656/**
4393 * si_vm_set_page - update the page tables using the CP 4657 * si_vm_set_page - update the page tables using the CP
4394 * 4658 *
4395 * @rdev: radeon_device pointer 4659 * @rdev: radeon_device pointer
@@ -5755,6 +6019,7 @@ int si_irq_process(struct radeon_device *rdev)
5755 u32 ring_index; 6019 u32 ring_index;
5756 bool queue_hotplug = false; 6020 bool queue_hotplug = false;
5757 bool queue_thermal = false; 6021 bool queue_thermal = false;
6022 u32 status, addr;
5758 6023
5759 if (!rdev->ih.enabled || rdev->shutdown) 6024 if (!rdev->ih.enabled || rdev->shutdown)
5760 return IRQ_NONE; 6025 return IRQ_NONE;
@@ -5990,11 +6255,14 @@ restart_ih:
5990 break; 6255 break;
5991 case 146: 6256 case 146:
5992 case 147: 6257 case 147:
6258 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
6259 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
5993 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); 6260 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
5994 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 6261 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
5995 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 6262 addr);
5996 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 6263 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
5997 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 6264 status);
6265 si_vm_decode_fault(rdev, status, addr);
5998 /* reset addr and status */ 6266 /* reset addr and status */
5999 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); 6267 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
6000 break; 6268 break;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 11:32:55 -0400