diff options
author | David S. Miller <davem@davemloft.net> | 2014-09-08 00:41:53 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2014-09-08 00:41:53 -0400 |
commit | eb84d6b60491a3ca3d90d62ee5346b007770d40d (patch) | |
tree | 22aadf9ada15e1ae5ba4c400aafab6f2541996e6 /drivers/gpu/drm/radeon/si.c | |
parent | 97a13e5289baa96eaddd06e61d277457d837af3a (diff) | |
parent | d030671f3f261e528dc6e396a13f10859a74ae7c (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 40 |
1 files changed, 27 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 011779bd2b3d..6bce40847753 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -3057,7 +3057,7 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
3057 | u32 sx_debug_1; | 3057 | u32 sx_debug_1; |
3058 | u32 hdp_host_path_cntl; | 3058 | u32 hdp_host_path_cntl; |
3059 | u32 tmp; | 3059 | u32 tmp; |
3060 | int i, j, k; | 3060 | int i, j; |
3061 | 3061 | ||
3062 | switch (rdev->family) { | 3062 | switch (rdev->family) { |
3063 | case CHIP_TAHITI: | 3063 | case CHIP_TAHITI: |
@@ -3255,12 +3255,11 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
3255 | rdev->config.si.max_sh_per_se, | 3255 | rdev->config.si.max_sh_per_se, |
3256 | rdev->config.si.max_cu_per_sh); | 3256 | rdev->config.si.max_cu_per_sh); |
3257 | 3257 | ||
3258 | rdev->config.si.active_cus = 0; | ||
3258 | for (i = 0; i < rdev->config.si.max_shader_engines; i++) { | 3259 | for (i = 0; i < rdev->config.si.max_shader_engines; i++) { |
3259 | for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { | 3260 | for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { |
3260 | for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { | 3261 | rdev->config.si.active_cus += |
3261 | rdev->config.si.active_cus += | 3262 | hweight32(si_get_cu_active_bitmap(rdev, i, j)); |
3262 | hweight32(si_get_cu_active_bitmap(rdev, i, j)); | ||
3263 | } | ||
3264 | } | 3263 | } |
3265 | } | 3264 | } |
3266 | 3265 | ||
@@ -3541,7 +3540,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
3541 | radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); | 3540 | radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); |
3542 | radeon_ring_write(ring, 0xc000); | 3541 | radeon_ring_write(ring, 0xc000); |
3543 | radeon_ring_write(ring, 0xe000); | 3542 | radeon_ring_write(ring, 0xe000); |
3544 | radeon_ring_unlock_commit(rdev, ring); | 3543 | radeon_ring_unlock_commit(rdev, ring, false); |
3545 | 3544 | ||
3546 | si_cp_enable(rdev, true); | 3545 | si_cp_enable(rdev, true); |
3547 | 3546 | ||
@@ -3570,7 +3569,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
3570 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | 3569 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
3571 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ | 3570 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ |
3572 | 3571 | ||
3573 | radeon_ring_unlock_commit(rdev, ring); | 3572 | radeon_ring_unlock_commit(rdev, ring, false); |
3574 | 3573 | ||
3575 | for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { | 3574 | for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { |
3576 | ring = &rdev->ring[i]; | 3575 | ring = &rdev->ring[i]; |
@@ -3580,7 +3579,7 @@ static int si_cp_start(struct radeon_device *rdev) | |||
3580 | radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); | 3579 | radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); |
3581 | radeon_ring_write(ring, 0); | 3580 | radeon_ring_write(ring, 0); |
3582 | 3581 | ||
3583 | radeon_ring_unlock_commit(rdev, ring); | 3582 | radeon_ring_unlock_commit(rdev, ring, false); |
3584 | } | 3583 | } |
3585 | 3584 | ||
3586 | return 0; | 3585 | return 0; |
@@ -4291,10 +4290,10 @@ static int si_pcie_gart_enable(struct radeon_device *rdev) | |||
4291 | for (i = 1; i < 16; i++) { | 4290 | for (i = 1; i < 16; i++) { |
4292 | if (i < 8) | 4291 | if (i < 8) |
4293 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), | 4292 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), |
4294 | rdev->gart.table_addr >> 12); | 4293 | rdev->vm_manager.saved_table_addr[i]); |
4295 | else | 4294 | else |
4296 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), | 4295 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), |
4297 | rdev->gart.table_addr >> 12); | 4296 | rdev->vm_manager.saved_table_addr[i]); |
4298 | } | 4297 | } |
4299 | 4298 | ||
4300 | /* enable context1-15 */ | 4299 | /* enable context1-15 */ |
@@ -4326,6 +4325,17 @@ static int si_pcie_gart_enable(struct radeon_device *rdev) | |||
4326 | 4325 | ||
4327 | static void si_pcie_gart_disable(struct radeon_device *rdev) | 4326 | static void si_pcie_gart_disable(struct radeon_device *rdev) |
4328 | { | 4327 | { |
4328 | unsigned i; | ||
4329 | |||
4330 | for (i = 1; i < 16; ++i) { | ||
4331 | uint32_t reg; | ||
4332 | if (i < 8) | ||
4333 | reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2); | ||
4334 | else | ||
4335 | reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2); | ||
4336 | rdev->vm_manager.saved_table_addr[i] = RREG32(reg); | ||
4337 | } | ||
4338 | |||
4329 | /* Disable all tables */ | 4339 | /* Disable all tables */ |
4330 | WREG32(VM_CONTEXT0_CNTL, 0); | 4340 | WREG32(VM_CONTEXT0_CNTL, 0); |
4331 | WREG32(VM_CONTEXT1_CNTL, 0); | 4341 | WREG32(VM_CONTEXT1_CNTL, 0); |
@@ -5028,7 +5038,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5028 | 5038 | ||
5029 | /* flush hdp cache */ | 5039 | /* flush hdp cache */ |
5030 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5040 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5031 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5041 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
5032 | WRITE_DATA_DST_SEL(0))); | 5042 | WRITE_DATA_DST_SEL(0))); |
5033 | radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); | 5043 | radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); |
5034 | radeon_ring_write(ring, 0); | 5044 | radeon_ring_write(ring, 0); |
@@ -5036,7 +5046,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | |||
5036 | 5046 | ||
5037 | /* bits 0-15 are the VM contexts0-15 */ | 5047 | /* bits 0-15 are the VM contexts0-15 */ |
5038 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | 5048 | radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5039 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | 5049 | radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
5040 | WRITE_DATA_DST_SEL(0))); | 5050 | WRITE_DATA_DST_SEL(0))); |
5041 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | 5051 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
5042 | radeon_ring_write(ring, 0); | 5052 | radeon_ring_write(ring, 0); |
@@ -7178,6 +7188,9 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) | |||
7178 | int ret, i; | 7188 | int ret, i; |
7179 | u16 tmp16; | 7189 | u16 tmp16; |
7180 | 7190 | ||
7191 | if (pci_is_root_bus(rdev->pdev->bus)) | ||
7192 | return; | ||
7193 | |||
7181 | if (radeon_pcie_gen2 == 0) | 7194 | if (radeon_pcie_gen2 == 0) |
7182 | return; | 7195 | return; |
7183 | 7196 | ||
@@ -7455,7 +7468,8 @@ static void si_program_aspm(struct radeon_device *rdev) | |||
7455 | if (orig != data) | 7468 | if (orig != data) |
7456 | WREG32_PIF_PHY1(PB1_PIF_CNTL, data); | 7469 | WREG32_PIF_PHY1(PB1_PIF_CNTL, data); |
7457 | 7470 | ||
7458 | if (!disable_clkreq) { | 7471 | if (!disable_clkreq && |
7472 | !pci_is_root_bus(rdev->pdev->bus)) { | ||
7459 | struct pci_dev *root = rdev->pdev->bus->self; | 7473 | struct pci_dev *root = rdev->pdev->bus->self; |
7460 | u32 lnkcap; | 7474 | u32 lnkcap; |
7461 | 7475 | ||