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authorAlex Deucher <alexander.deucher@amd.com>2013-04-17 17:53:50 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-30 16:30:08 -0400
commit1fd11777c2f0e6b6b37432b984bf40e3c6072f23 (patch)
tree28bfbbcfb8c821ba2a1c23c67b52f8f43fabc43f /drivers/gpu/drm/radeon/si.c
parent10b7ca7e09aa0d5f90265f130aee2b9270bfaadc (diff)
drm/radeon: convert SI,CIK to use sumo_rlc functions
and remove duplicate si_rlc functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c174
1 files changed, 11 insertions, 163 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 610adfc86bea..8b8963d4a732 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -68,6 +68,8 @@ MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
68 68
69static void si_pcie_gen3_enable(struct radeon_device *rdev); 69static void si_pcie_gen3_enable(struct radeon_device *rdev);
70static void si_program_aspm(struct radeon_device *rdev); 70static void si_program_aspm(struct radeon_device *rdev);
71extern void sumo_rlc_fini(struct radeon_device *rdev);
72extern int sumo_rlc_init(struct radeon_device *rdev);
71extern int r600_ih_ring_alloc(struct radeon_device *rdev); 73extern int r600_ih_ring_alloc(struct radeon_device *rdev);
72extern void r600_ih_ring_fini(struct radeon_device *rdev); 74extern void r600_ih_ring_fini(struct radeon_device *rdev);
73extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 75extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
@@ -5275,166 +5277,6 @@ static void si_fini_pg(struct radeon_device *rdev)
5275/* 5277/*
5276 * RLC 5278 * RLC
5277 */ 5279 */
5278void si_rlc_fini(struct radeon_device *rdev)
5279{
5280 int r;
5281
5282 /* save restore block */
5283 if (rdev->rlc.save_restore_obj) {
5284 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
5285 if (unlikely(r != 0))
5286 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
5287 radeon_bo_unpin(rdev->rlc.save_restore_obj);
5288 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
5289
5290 radeon_bo_unref(&rdev->rlc.save_restore_obj);
5291 rdev->rlc.save_restore_obj = NULL;
5292 }
5293
5294 /* clear state block */
5295 if (rdev->rlc.clear_state_obj) {
5296 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
5297 if (unlikely(r != 0))
5298 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
5299 radeon_bo_unpin(rdev->rlc.clear_state_obj);
5300 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
5301
5302 radeon_bo_unref(&rdev->rlc.clear_state_obj);
5303 rdev->rlc.clear_state_obj = NULL;
5304 }
5305}
5306
5307#define RLC_CLEAR_STATE_END_MARKER 0x00000001
5308
5309int si_rlc_init(struct radeon_device *rdev)
5310{
5311 volatile u32 *dst_ptr;
5312 u32 dws, data, i, j, k, reg_num;
5313 u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index;
5314 u64 reg_list_mc_addr;
5315 const struct cs_section_def *cs_data = si_cs_data;
5316 int r;
5317
5318 /* save restore block */
5319 if (rdev->rlc.save_restore_obj == NULL) {
5320 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
5321 RADEON_GEM_DOMAIN_VRAM, NULL,
5322 &rdev->rlc.save_restore_obj);
5323 if (r) {
5324 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
5325 return r;
5326 }
5327 }
5328
5329 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
5330 if (unlikely(r != 0)) {
5331 si_rlc_fini(rdev);
5332 return r;
5333 }
5334 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
5335 &rdev->rlc.save_restore_gpu_addr);
5336 if (r) {
5337 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
5338 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
5339 si_rlc_fini(rdev);
5340 return r;
5341 }
5342
5343 if (rdev->family == CHIP_VERDE) {
5344 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
5345 if (r) {
5346 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
5347 si_rlc_fini(rdev);
5348 return r;
5349 }
5350 /* write the sr buffer */
5351 dst_ptr = rdev->rlc.sr_ptr;
5352 for (i = 0; i < ARRAY_SIZE(verde_rlc_save_restore_register_list); i++) {
5353 dst_ptr[i] = verde_rlc_save_restore_register_list[i];
5354 }
5355 radeon_bo_kunmap(rdev->rlc.save_restore_obj);
5356 }
5357 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
5358
5359 /* clear state block */
5360 reg_list_num = 0;
5361 dws = 0;
5362 for (i = 0; cs_data[i].section != NULL; i++) {
5363 for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
5364 reg_list_num++;
5365 dws += cs_data[i].section[j].reg_count;
5366 }
5367 }
5368 reg_list_blk_index = (3 * reg_list_num + 2);
5369 dws += reg_list_blk_index;
5370
5371 if (rdev->rlc.clear_state_obj == NULL) {
5372 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
5373 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
5374 if (r) {
5375 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
5376 si_rlc_fini(rdev);
5377 return r;
5378 }
5379 }
5380 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
5381 if (unlikely(r != 0)) {
5382 si_rlc_fini(rdev);
5383 return r;
5384 }
5385 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
5386 &rdev->rlc.clear_state_gpu_addr);
5387 if (r) {
5388
5389 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
5390 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
5391 si_rlc_fini(rdev);
5392 return r;
5393 }
5394 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
5395 if (r) {
5396 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
5397 si_rlc_fini(rdev);
5398 return r;
5399 }
5400 /* set up the cs buffer */
5401 dst_ptr = rdev->rlc.cs_ptr;
5402 reg_list_hdr_blk_index = 0;
5403 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
5404 data = upper_32_bits(reg_list_mc_addr);
5405 dst_ptr[reg_list_hdr_blk_index] = data;
5406 reg_list_hdr_blk_index++;
5407 for (i = 0; cs_data[i].section != NULL; i++) {
5408 for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
5409 reg_num = cs_data[i].section[j].reg_count;
5410 data = reg_list_mc_addr & 0xffffffff;
5411 dst_ptr[reg_list_hdr_blk_index] = data;
5412 reg_list_hdr_blk_index++;
5413
5414 data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
5415 dst_ptr[reg_list_hdr_blk_index] = data;
5416 reg_list_hdr_blk_index++;
5417
5418 data = 0x08000000 | (reg_num * 4);
5419 dst_ptr[reg_list_hdr_blk_index] = data;
5420 reg_list_hdr_blk_index++;
5421
5422 for (k = 0; k < reg_num; k++) {
5423 data = cs_data[i].section[j].extent[k];
5424 dst_ptr[reg_list_blk_index + k] = data;
5425 }
5426 reg_list_mc_addr += reg_num * 4;
5427 reg_list_blk_index += reg_num;
5428 }
5429 }
5430 dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
5431
5432 radeon_bo_kunmap(rdev->rlc.clear_state_obj);
5433 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
5434
5435 return 0;
5436}
5437
5438void si_rlc_reset(struct radeon_device *rdev) 5280void si_rlc_reset(struct radeon_device *rdev)
5439{ 5281{
5440 u32 tmp = RREG32(GRBM_SOFT_RESET); 5282 u32 tmp = RREG32(GRBM_SOFT_RESET);
@@ -6449,7 +6291,13 @@ static int si_startup(struct radeon_device *rdev)
6449 si_gpu_init(rdev); 6291 si_gpu_init(rdev);
6450 6292
6451 /* allocate rlc buffers */ 6293 /* allocate rlc buffers */
6452 r = si_rlc_init(rdev); 6294 if (rdev->family == CHIP_VERDE) {
6295 rdev->rlc.reg_list = verde_rlc_save_restore_register_list;
6296 rdev->rlc.reg_list_size =
6297 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
6298 }
6299 rdev->rlc.cs_data = si_cs_data;
6300 r = sumo_rlc_init(rdev);
6453 if (r) { 6301 if (r) {
6454 DRM_ERROR("Failed to init rlc BOs!\n"); 6302 DRM_ERROR("Failed to init rlc BOs!\n");
6455 return r; 6303 return r;
@@ -6735,7 +6583,7 @@ int si_init(struct radeon_device *rdev)
6735 si_cp_fini(rdev); 6583 si_cp_fini(rdev);
6736 cayman_dma_fini(rdev); 6584 cayman_dma_fini(rdev);
6737 si_irq_fini(rdev); 6585 si_irq_fini(rdev);
6738 si_rlc_fini(rdev); 6586 sumo_rlc_fini(rdev);
6739 radeon_wb_fini(rdev); 6587 radeon_wb_fini(rdev);
6740 radeon_ib_pool_fini(rdev); 6588 radeon_ib_pool_fini(rdev);
6741 radeon_vm_manager_fini(rdev); 6589 radeon_vm_manager_fini(rdev);
@@ -6761,7 +6609,7 @@ void si_fini(struct radeon_device *rdev)
6761 si_cp_fini(rdev); 6609 si_cp_fini(rdev);
6762 cayman_dma_fini(rdev); 6610 cayman_dma_fini(rdev);
6763 si_irq_fini(rdev); 6611 si_irq_fini(rdev);
6764 si_rlc_fini(rdev); 6612 sumo_rlc_fini(rdev);
6765 si_fini_cg(rdev); 6613 si_fini_cg(rdev);
6766 si_fini_pg(rdev); 6614 si_fini_pg(rdev);
6767 radeon_wb_fini(rdev); 6615 radeon_wb_fini(rdev);