Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master

1 files changed, 57 insertions, 39 deletions

diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index ba68c9fe90a1..9035121f4b58 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -26,9 +26,11 @@
  *          Jerome Glisse
  */
 #include <linux/seq_file.h>
+#include <linux/slab.h>
 #include "drmP.h"
 #include "rv515d.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "rv515_reg_safe.h"
 
@@ -277,19 +279,15 @@ static void rv515_vram_get_type(struct radeon_device *rdev)
         }
 }
 
-void rv515_vram_info(struct radeon_device *rdev)
+void rv515_mc_init(struct radeon_device *rdev)
 {
-        fixed20_12 a;
 
         rv515_vram_get_type(rdev);
-
         r100_vram_init_sizes(rdev);
-        /* FIXME: we should enforce default clock in case GPU is not in
-         * default setup
-         */
-        a.full = rfixed_const(100);
-        rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-        rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+        radeon_vram_location(rdev, &rdev->mc, 0);
+        if (!(rdev->flags & RADEON_IS_AGP))
+                radeon_gtt_location(rdev, &rdev->mc);
+        radeon_update_bandwidth_info(rdev);
 }
 
 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -478,8 +476,8 @@ static int rv515_startup(struct radeon_device *rdev)
                         return r;
         }
         /* Enable IRQ */
-        rdev->irq.sw_int = true;
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -514,6 +512,8 @@ int rv515_resume(struct radeon_device *rdev)
         atom_asic_init(rdev->mode_info.atom_context);
         /* Resume clock after posting */
         rv515_clock_startup(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
         return rv515_startup(rdev);
 }
 
@@ -535,16 +535,16 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
 
 void rv515_fini(struct radeon_device *rdev)
 {
-        rv515_suspend(rdev);
+        radeon_pm_fini(rdev);
         r100_cp_fini(rdev);
         r100_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
-    rv370_pcie_gart_fini(rdev);
+        rv370_pcie_gart_fini(rdev);
         radeon_agp_fini(rdev);
         radeon_irq_kms_fini(rdev);
         radeon_fence_driver_fini(rdev);
-        radeon_object_fini(rdev);
+        radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
         kfree(rdev->bios);
         rdev->bios = NULL;
@@ -580,20 +580,21 @@ int rv515_init(struct radeon_device *rdev)
                         RREG32(R_0007C0_CP_STAT));
         }
         /* check if cards are posted or not */
-        if (!radeon_card_posted(rdev) && rdev->bios) {
-                DRM_INFO("GPU not posted. posting now...\n");
-                atom_asic_init(rdev->mode_info.atom_context);
-        }
+        if (radeon_boot_test_post_card(rdev) == false)
+                return -EINVAL;
         /* Initialize clocks */
         radeon_get_clock_info(rdev->ddev);
         /* Initialize power management */
         radeon_pm_init(rdev);
-        /* Get vram informations */
-        rv515_vram_info(rdev);
-        /* Initialize memory controller (also test AGP) */
-        r = r420_mc_init(rdev);
-        if (r)
-                return r;
+        /* initialize AGP */
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r) {
+                        radeon_agp_disable(rdev);
+                }
+        }
+        /* initialize memory controller */
+        rv515_mc_init(rdev);
         rv515_debugfs(rdev);
         /* Fence driver */
         r = radeon_fence_driver_init(rdev);
@@ -603,7 +604,7 @@ int rv515_init(struct radeon_device *rdev)
         if (r)
                 return r;
         /* Memory manager */
-        r = radeon_object_init(rdev);
+        r = radeon_bo_init(rdev);
         if (r)
                 return r;
         r = rv370_pcie_gart_init(rdev);
@@ -615,13 +616,12 @@ int rv515_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                rv515_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
+                radeon_irq_kms_fini(rdev);
                 rv370_pcie_gart_fini(rdev);
                 radeon_agp_fini(rdev);
-                radeon_irq_kms_fini(rdev);
                 rdev->accel_working = false;
         }
         return 0;
@@ -892,8 +892,9 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 
         b.full = rfixed_const(mode->crtc_hdisplay);
         c.full = rfixed_const(256);
-        a.full = rfixed_mul(wm->num_line_pair, b);
-        request_fifo_depth.full = rfixed_div(a, c);
+        a.full = rfixed_div(b, c);
+        request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
+        request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
         if (a.full < rfixed_const(4)) {
                 wm->lb_request_fifo_depth = 4;
         } else {
@@ -995,15 +996,17 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
         a.full = rfixed_const(16);
         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
+        wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
 
         /* Determine estimated width */
         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
         estimated_width.full = rfixed_div(estimated_width, consumption_time);
         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
-                wm->priority_mark.full = rfixed_const(10);
+                wm->priority_mark.full = wm->priority_mark_max.full;
         } else {
                 a.full = rfixed_const(16);
                 wm->priority_mark.full = rfixed_div(estimated_width, a);
+                wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
         }
 }
@@ -1014,7 +1017,7 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
         struct drm_display_mode *mode1 = NULL;
         struct rv515_watermark wm0;
         struct rv515_watermark wm1;
-        u32 tmp;
+        u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
         fixed20_12 priority_mark02, priority_mark12, fill_rate;
         fixed20_12 a, b;
 
@@ -1082,10 +1085,16 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
                         priority_mark12.full = 0;
                 if (wm1.priority_mark_max.full > priority_mark12.full)
                         priority_mark12.full = wm1.priority_mark_max.full;
-                WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
-                WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
-                WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
-                WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
+                d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
+                d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
+                if (rdev->disp_priority == 2) {
+                        d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+                        d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+                }
+                WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+                WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
+                WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
+                WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
         } else if (mode0) {
                 if (rfixed_trunc(wm0.dbpp) > 64)
                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
@@ -1112,8 +1121,11 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
                         priority_mark02.full = 0;
                 if (wm0.priority_mark_max.full > priority_mark02.full)
                         priority_mark02.full = wm0.priority_mark_max.full;
-                WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
-                WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
+                d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
+                if (rdev->disp_priority == 2)
+                        d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
+                WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+                WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
                 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
                 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
         } else {
@@ -1142,10 +1154,13 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
                         priority_mark12.full = 0;
                 if (wm1.priority_mark_max.full > priority_mark12.full)
                         priority_mark12.full = wm1.priority_mark_max.full;
+                d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
+                if (rdev->disp_priority == 2)
+                        d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
                 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
                 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
-                WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
-                WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
+                WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
+                WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
         }
 }
 
@@ -1155,6 +1170,8 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
         struct drm_display_mode *mode0 = NULL;
         struct drm_display_mode *mode1 = NULL;
 
+        radeon_update_display_priority(rdev);
+
         if (rdev->mode_info.crtcs[0]->base.enabled)
                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
         if (rdev->mode_info.crtcs[1]->base.enabled)
@@ -1164,7 +1181,8 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
          * modes if the user specifies HIGH for displaypriority
          * option.
          */
-        if (rdev->disp_priority == 2) {
+        if ((rdev->disp_priority == 2) &&
+            (rdev->family == CHIP_RV515)) {
                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;