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authorAlex Deucher <alexdeucher@gmail.com>2010-03-18 01:04:01 -0400
committerDave Airlie <airlied@redhat.com>2010-03-30 23:11:29 -0400
commita084e6ee6e64a76f1a9665d527203cdab7d6048f (patch)
treeebc1f90b7111b39bee17ff3f1e2ee02452dc1bf7 /drivers/gpu/drm/radeon/rs690.c
parentc1bcad9d16831859373d8f579fa1e146409f9960 (diff)
drm/radeon/kms/atom: make sure tables are valid (v2)
Check that atom cmd and data tables are valid before using them. (v2) - fix some whitespace errors noticed by Rafał Miłecki - check a few more cases Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rs690.c')
-rw-r--r--drivers/gpu/drm/radeon/rs690.c74
1 files changed, 44 insertions, 30 deletions
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index e356935b0283..f758d5cc1160 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -58,42 +58,57 @@ static void rs690_gpu_init(struct radeon_device *rdev)
58 } 58 }
59} 59}
60 60
61union igp_info {
62 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
63 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
64};
65
61void rs690_pm_info(struct radeon_device *rdev) 66void rs690_pm_info(struct radeon_device *rdev)
62{ 67{
63 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 68 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
64 struct _ATOM_INTEGRATED_SYSTEM_INFO *info; 69 union igp_info *info;
65 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
66 void *ptr;
67 uint16_t data_offset; 70 uint16_t data_offset;
68 uint8_t frev, crev; 71 uint8_t frev, crev;
69 fixed20_12 tmp; 72 fixed20_12 tmp;
70 73
71 atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 74 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
72 &frev, &crev, &data_offset); 75 &frev, &crev, &data_offset)) {
73 ptr = rdev->mode_info.atom_context->bios + data_offset; 76 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
74 info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr; 77
75 info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr; 78 /* Get various system informations from bios */
76 /* Get various system informations from bios */ 79 switch (crev) {
77 switch (crev) { 80 case 1:
78 case 1: 81 tmp.full = rfixed_const(100);
79 tmp.full = rfixed_const(100); 82 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock);
80 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock); 83 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
81 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); 84 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
82 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock)); 85 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock));
83 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock)); 86 rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth);
84 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth); 87 break;
85 break; 88 case 2:
86 case 2: 89 tmp.full = rfixed_const(100);
87 tmp.full = rfixed_const(100); 90 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock);
88 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock); 91 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
89 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); 92 rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock);
90 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock); 93 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
91 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); 94 rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq);
92 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq); 95 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
93 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp); 96 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
94 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth)); 97 break;
95 break; 98 default:
96 default: 99 tmp.full = rfixed_const(100);
100 /* We assume the slower possible clock ie worst case */
101 /* DDR 333Mhz */
102 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
103 /* FIXME: system clock ? */
104 rdev->pm.igp_system_mclk.full = rfixed_const(100);
105 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
106 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
107 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
108 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
109 break;
110 }
111 } else {
97 tmp.full = rfixed_const(100); 112 tmp.full = rfixed_const(100);
98 /* We assume the slower possible clock ie worst case */ 113 /* We assume the slower possible clock ie worst case */
99 /* DDR 333Mhz */ 114 /* DDR 333Mhz */
@@ -104,7 +119,6 @@ void rs690_pm_info(struct radeon_device *rdev)
104 rdev->pm.igp_ht_link_clk.full = rfixed_const(200); 119 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
105 rdev->pm.igp_ht_link_width.full = rfixed_const(8); 120 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
106 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 121 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
107 break;
108 } 122 }
109 /* Compute various bandwidth */ 123 /* Compute various bandwidth */
110 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 124 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */