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authorSascha Hauer <s.hauer@pengutronix.de>2011-02-11 02:32:18 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2011-02-11 02:33:14 -0500
commitf19693a17c6705e197eb24d4618060eaac1b535c (patch)
treefc39dc23297c0e6be730cb0dfd74a34d9c0b8bfd /drivers/gpu/drm/radeon/radeon_mode.h
parent23b120cdfae4f5c29da69de750d545bad719ead4 (diff)
parent100b33c8bd8a3235fd0b7948338d6cbb3db3c63d (diff)
Merge commit 'v2.6.38-rc4' into imx-for-2.6.39
Conflicts: arch/arm/mach-mxs/clock-mx28.c Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h23
1 files changed, 16 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 12bdeab91c86..6794cdf91f28 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -149,6 +149,7 @@ struct radeon_tmds_pll {
149#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
150#define RADEON_PLL_USE_POST_DIV (1 << 12) 150#define RADEON_PLL_USE_POST_DIV (1 << 12)
151#define RADEON_PLL_IS_LCD (1 << 13) 151#define RADEON_PLL_IS_LCD (1 << 13)
152#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
152 153
153struct radeon_pll { 154struct radeon_pll {
154 /* reference frequency */ 155 /* reference frequency */
@@ -510,13 +511,21 @@ extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
510 struct radeon_atom_ss *ss, 511 struct radeon_atom_ss *ss,
511 int id, u32 clock); 512 int id, u32 clock);
512 513
513extern void radeon_compute_pll(struct radeon_pll *pll, 514extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
514 uint64_t freq, 515 uint64_t freq,
515 uint32_t *dot_clock_p, 516 uint32_t *dot_clock_p,
516 uint32_t *fb_div_p, 517 uint32_t *fb_div_p,
517 uint32_t *frac_fb_div_p, 518 uint32_t *frac_fb_div_p,
518 uint32_t *ref_div_p, 519 uint32_t *ref_div_p,
519 uint32_t *post_div_p); 520 uint32_t *post_div_p);
521
522extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
523 u32 freq,
524 u32 *dot_clock_p,
525 u32 *fb_div_p,
526 u32 *frac_fb_div_p,
527 u32 *ref_div_p,
528 u32 *post_div_p);
520 529
521extern void radeon_setup_encoder_clones(struct drm_device *dev); 530extern void radeon_setup_encoder_clones(struct drm_device *dev);
522 531