drm/radeon: handle ss percentage divider properly

It's either 100 or 1000 depending on the flags in the
table.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 28bba631b80c..7c53fb1cc46d 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -291,6 +291,7 @@ struct radeon_tv_regs {
 
 struct radeon_atom_ss {
         uint16_t percentage;
+        uint16_t percentage_divider;
         uint8_t type;
         uint16_t step;
         uint8_t delay;