DRM/radeon: For single CRTC GPUs move handling of CRTC_CRT_ON to crtc_dpms().

On all dual CRTC GPUs the CRTC_CRT_ON in the RADEON_CRTC_EXT_CNTL register
 controls the CRTC of the primary DAC. Therefore it is set in the DAC DMPS
function.
This is different for GPU's with a single CRTC but a primary and a
TV DAC: here it controls the single CRTC no matter where it is routed.
Therefore we set it here. This avoids an elaborate on/off state tracking
since both primary_dac_dpms() and tv_dac_dpms() functions would have
to touch this bit.
On single CRTC GPUs with just one DAC it's irrelevant where this bit
is handled.

agd5f: fix warning

Signed-off-by: Egbert Eich <eich@suse.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 5 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 3afed70306df..817392fc2d04 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -537,7 +537,9 @@ static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode
                 break;
         }
 
-        WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
+        /* handled in radeon_crtc_dpms() */
+        if (!(rdev->flags & RADEON_SINGLE_CRTC))
+                WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
         WREG32(RADEON_DAC_CNTL, dac_cntl);
         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 
@@ -1095,7 +1097,8 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
         } else {
                 if (is_tv)
                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
-                else
+                /* handled in radeon_crtc_dpms() */
+                else if (!(rdev->flags & RADEON_SINGLE_CRTC))
                         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
         }