Merge remote branch 'korg/drm-radeon-testing' into drm-next-stage

* korg/drm-radeon-testing: (62 commits)
  drm/radeon/kms: update new pll algo
  drm/radeon/kms: add support for square microtiles on r3xx-r5xx
  drm/radeon/kms: force pinning buffer into visible VRAM
  drm/radeon/kms/evergreen: fix typo in cursor code
  drm/radeon/kms: implement reading active PCIE lanes on R600+
  drm/radeon/kms: for downclocking non-mobility check PERFORMANCE state
  drm/radeon/kms: simplify storing current and requested PM mode
  drm/radeon: fixes for r6xx/r7xx gfx init
  drm/radeon/rv740: fix backend setup
  drm/radeon/kms: fix R3XX/R4XX memory controller initialization
  [rfc] drm/radeon/kms: pm debugging check for vbl.
  drm/radeon: Fix memory allocation failures in the preKMS command stream checking.
  drm: Add generic multipart buffer.
  drm/radeon/kms: simplify memory controller setup V2
  drm/radeon: Add asic hook for dma copy to r200 cards.
  drm/radeon/kms: Create asic structure for r300 pcie cards.
  drm/radeon/kms: remove unused r600_gart_clear_page
  drm/radeon/kms: remove HDP flushes from fence emit (v2)
  drm/radeon/kms: add LVDS pll quirk for Dell Studio 15
  drm/radeon/kms: simplify picking power state
  ...

Conflicts:
	drivers/gpu/drm/radeon/atom.c
	drivers/gpu/drm/radeon/atombios.h
	drivers/gpu/drm/radeon/atombios_dp.c
	drivers/gpu/drm/radeon/r600.c
	drivers/gpu/drm/radeon/r600_audio.c
	drivers/gpu/drm/radeon/r600_cp.c
	drivers/gpu/drm/radeon/radeon.h
	drivers/gpu/drm/radeon/radeon_connectors.c
	drivers/gpu/drm/radeon/radeon_ring.c
	drivers/gpu/drm/radeon/rv770.c

1 files changed, 5 insertions, 24 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index b6d8081e1246..df23d6a01d02 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -403,7 +403,7 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 
         /* if scanout was in GTT this really wouldn't work */
         /* crtc offset is from display base addr not FB location */
-        radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
+        radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 
         base -= radeon_crtc->legacy_display_base_addr;
 
@@ -582,29 +582,6 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
                                    ? RADEON_CRTC_V_SYNC_POL
                                    : 0));
 
-        /* TODO -> Dell Server */
-        if (0) {
-                uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
-                uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
-                uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
-                uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
-
-                dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
-                dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
-
-                /* For CRT on DAC2, don't turn it on if BIOS didn't
-                   enable it, even it's detected.
-                */
-                disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
-                tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
-                tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
-
-                WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
-                WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
-                WREG32(RADEON_DAC_CNTL2, dac2_cntl);
-                WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
-        }
-
         if (radeon_crtc->crtc_id) {
                 uint32_t crtc2_gen_cntl;
                 uint32_t disp2_merge_cntl;
@@ -726,6 +703,10 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                 pll = &rdev->clock.p1pll;
 
         pll->flags = RADEON_PLL_LEGACY;
+        if (radeon_new_pll == 1)
+                pll->algo = PLL_ALGO_NEW;
+        else
+                pll->algo = PLL_ALGO_LEGACY;
 
         if (mode->clock > 200000) /* range limits??? */
                 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;