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authorAlex Deucher <alexdeucher@gmail.com>2010-03-11 10:38:07 -0500
committerDave Airlie <airlied@redhat.com>2010-03-14 19:59:24 -0400
commitd805f50aa1d9eef63fec356b2be557e2da3cd643 (patch)
tree7f1fd600fc3c9be78b40dac15cf3e6aa8eec7bc1 /drivers/gpu/drm/radeon/radeon_legacy_crtc.c
parentb28ea41164dc36110dafcdc63783e9b7fb865784 (diff)
drm/radeon/kms/rs4xx: make sure crtcs are enabled when setting timing
based on ddx patch from Matthias Hopf. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_legacy_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index df23d6a01d02..88865e38fe30 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -603,6 +603,10 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
603 ? RADEON_CRTC2_INTERLACE_EN 603 ? RADEON_CRTC2_INTERLACE_EN
604 : 0)); 604 : 0));
605 605
606 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
607 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
608 crtc2_gen_cntl |= RADEON_CRTC2_EN;
609
606 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 610 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
607 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 611 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
608 612
@@ -630,6 +634,10 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
630 ? RADEON_CRTC_INTERLACE_EN 634 ? RADEON_CRTC_INTERLACE_EN
631 : 0)); 635 : 0));
632 636
637 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
638 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
639 crtc_gen_cntl |= RADEON_CRTC_EN;
640
633 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 641 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
634 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 642 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
635 RADEON_CRTC_VSYNC_DIS | 643 RADEON_CRTC_VSYNC_DIS |