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authorDaniel Vetter <daniel.vetter@ffwll.ch>2010-03-11 16:19:14 -0500
committerDave Airlie <airlied@redhat.com>2010-03-14 21:27:03 -0400
commit0a10c85129c2d53cfd6db81677628e2fe58b5928 (patch)
tree6dd3dce247ad005d0ebb41b321cb7f0586e4bee0 /drivers/gpu/drm/radeon/radeon_device.c
parent1fc59eda33e55f8787901e3501d695bf5ecec48b (diff)
drm/radeon: create radeon_asic.c
And move asic init plus a few related functions from radeon_device.c to it. This file will hold all the asic structures in the future, but atm they're still stuck in radeon_asic.h. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_device.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c199
1 files changed, 0 insertions, 199 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e28e4ed5f720..581b75ad6ce7 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -33,7 +33,6 @@
33#include <linux/vga_switcheroo.h> 33#include <linux/vga_switcheroo.h>
34#include "radeon_reg.h" 34#include "radeon_reg.h"
35#include "radeon.h" 35#include "radeon.h"
36#include "radeon_asic.h"
37#include "atom.h" 36#include "atom.h"
38 37
39/* 38/*
@@ -288,181 +287,6 @@ void radeon_dummy_page_fini(struct radeon_device *rdev)
288} 287}
289 288
290 289
291/*
292 * Registers accessors functions.
293 */
294uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
295{
296 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
297 BUG_ON(1);
298 return 0;
299}
300
301void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
302{
303 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
304 reg, v);
305 BUG_ON(1);
306}
307
308void radeon_register_accessor_init(struct radeon_device *rdev)
309{
310 rdev->mc_rreg = &radeon_invalid_rreg;
311 rdev->mc_wreg = &radeon_invalid_wreg;
312 rdev->pll_rreg = &radeon_invalid_rreg;
313 rdev->pll_wreg = &radeon_invalid_wreg;
314 rdev->pciep_rreg = &radeon_invalid_rreg;
315 rdev->pciep_wreg = &radeon_invalid_wreg;
316
317 /* Don't change order as we are overridding accessor. */
318 if (rdev->family < CHIP_RV515) {
319 rdev->pcie_reg_mask = 0xff;
320 } else {
321 rdev->pcie_reg_mask = 0x7ff;
322 }
323 /* FIXME: not sure here */
324 if (rdev->family <= CHIP_R580) {
325 rdev->pll_rreg = &r100_pll_rreg;
326 rdev->pll_wreg = &r100_pll_wreg;
327 }
328 if (rdev->family >= CHIP_R420) {
329 rdev->mc_rreg = &r420_mc_rreg;
330 rdev->mc_wreg = &r420_mc_wreg;
331 }
332 if (rdev->family >= CHIP_RV515) {
333 rdev->mc_rreg = &rv515_mc_rreg;
334 rdev->mc_wreg = &rv515_mc_wreg;
335 }
336 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
337 rdev->mc_rreg = &rs400_mc_rreg;
338 rdev->mc_wreg = &rs400_mc_wreg;
339 }
340 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
341 rdev->mc_rreg = &rs690_mc_rreg;
342 rdev->mc_wreg = &rs690_mc_wreg;
343 }
344 if (rdev->family == CHIP_RS600) {
345 rdev->mc_rreg = &rs600_mc_rreg;
346 rdev->mc_wreg = &rs600_mc_wreg;
347 }
348 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
349 rdev->pciep_rreg = &r600_pciep_rreg;
350 rdev->pciep_wreg = &r600_pciep_wreg;
351 }
352}
353
354
355/*
356 * ASIC
357 */
358int radeon_asic_init(struct radeon_device *rdev)
359{
360 radeon_register_accessor_init(rdev);
361 switch (rdev->family) {
362 case CHIP_R100:
363 case CHIP_RV100:
364 case CHIP_RS100:
365 case CHIP_RV200:
366 case CHIP_RS200:
367 rdev->asic = &r100_asic;
368 break;
369 case CHIP_R200:
370 case CHIP_RV250:
371 case CHIP_RS300:
372 case CHIP_RV280:
373 rdev->asic = &r200_asic;
374 break;
375 case CHIP_R300:
376 case CHIP_R350:
377 case CHIP_RV350:
378 case CHIP_RV380:
379 if (rdev->flags & RADEON_IS_PCIE)
380 rdev->asic = &r300_asic_pcie;
381 else
382 rdev->asic = &r300_asic;
383 break;
384 case CHIP_R420:
385 case CHIP_R423:
386 case CHIP_RV410:
387 rdev->asic = &r420_asic;
388 break;
389 case CHIP_RS400:
390 case CHIP_RS480:
391 rdev->asic = &rs400_asic;
392 break;
393 case CHIP_RS600:
394 rdev->asic = &rs600_asic;
395 break;
396 case CHIP_RS690:
397 case CHIP_RS740:
398 rdev->asic = &rs690_asic;
399 break;
400 case CHIP_RV515:
401 rdev->asic = &rv515_asic;
402 break;
403 case CHIP_R520:
404 case CHIP_RV530:
405 case CHIP_RV560:
406 case CHIP_RV570:
407 case CHIP_R580:
408 rdev->asic = &r520_asic;
409 break;
410 case CHIP_R600:
411 case CHIP_RV610:
412 case CHIP_RV630:
413 case CHIP_RV620:
414 case CHIP_RV635:
415 case CHIP_RV670:
416 case CHIP_RS780:
417 case CHIP_RS880:
418 rdev->asic = &r600_asic;
419 break;
420 case CHIP_RV770:
421 case CHIP_RV730:
422 case CHIP_RV710:
423 case CHIP_RV740:
424 rdev->asic = &rv770_asic;
425 break;
426 case CHIP_CEDAR:
427 case CHIP_REDWOOD:
428 case CHIP_JUNIPER:
429 case CHIP_CYPRESS:
430 case CHIP_HEMLOCK:
431 rdev->asic = &evergreen_asic;
432 break;
433 default:
434 /* FIXME: not supported yet */
435 return -EINVAL;
436 }
437
438 if (rdev->flags & RADEON_IS_IGP) {
439 rdev->asic->get_memory_clock = NULL;
440 rdev->asic->set_memory_clock = NULL;
441 }
442
443 return 0;
444}
445
446
447/*
448 * Wrapper around modesetting bits.
449 */
450int radeon_clocks_init(struct radeon_device *rdev)
451{
452 int r;
453
454 r = radeon_static_clocks_init(rdev->ddev);
455 if (r) {
456 return r;
457 }
458 DRM_INFO("Clocks initialized !\n");
459 return 0;
460}
461
462void radeon_clocks_fini(struct radeon_device *rdev)
463{
464}
465
466/* ATOM accessor methods */ 290/* ATOM accessor methods */
467static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 291static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
468{ 292{
@@ -567,29 +391,6 @@ static unsigned int radeon_vga_set_decode(void *cookie, bool state)
567 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 391 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
568} 392}
569 393
570void radeon_agp_disable(struct radeon_device *rdev)
571{
572 rdev->flags &= ~RADEON_IS_AGP;
573 if (rdev->family >= CHIP_R600) {
574 DRM_INFO("Forcing AGP to PCIE mode\n");
575 rdev->flags |= RADEON_IS_PCIE;
576 } else if (rdev->family >= CHIP_RV515 ||
577 rdev->family == CHIP_RV380 ||
578 rdev->family == CHIP_RV410 ||
579 rdev->family == CHIP_R423) {
580 DRM_INFO("Forcing AGP to PCIE mode\n");
581 rdev->flags |= RADEON_IS_PCIE;
582 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
583 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
584 } else {
585 DRM_INFO("Forcing AGP to PCI mode\n");
586 rdev->flags |= RADEON_IS_PCI;
587 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
588 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
589 }
590 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
591}
592
593void radeon_check_arguments(struct radeon_device *rdev) 394void radeon_check_arguments(struct radeon_device *rdev)
594{ 395{
595 /* vramlimit must be a power of two */ 396 /* vramlimit must be a power of two */