Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master

1 files changed, 355 insertions, 266 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 41bb76fbe734..7b629e305560 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -26,15 +26,64 @@
  *          Jerome Glisse
  */
 #include <linux/console.h>
+#include <linux/slab.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/radeon_drm.h>
 #include <linux/vgaarb.h>
+#include <linux/vga_switcheroo.h>
 #include "radeon_reg.h"
 #include "radeon.h"
-#include "radeon_asic.h"
 #include "atom.h"
 
+static const char radeon_family_name[][16] = {
+        "R100",
+        "RV100",
+        "RS100",
+        "RV200",
+        "RS200",
+        "R200",
+        "RV250",
+        "RS300",
+        "RV280",
+        "R300",
+        "R350",
+        "RV350",
+        "RV380",
+        "R420",
+        "R423",
+        "RV410",
+        "RS400",
+        "RS480",
+        "RS600",
+        "RS690",
+        "RS740",
+        "RV515",
+        "R520",
+        "RV530",
+        "RV560",
+        "RV570",
+        "R580",
+        "R600",
+        "RV610",
+        "RV630",
+        "RV670",
+        "RV620",
+        "RV635",
+        "RS780",
+        "RS880",
+        "RV770",
+        "RV730",
+        "RV710",
+        "RV740",
+        "CEDAR",
+        "REDWOOD",
+        "JUNIPER",
+        "CYPRESS",
+        "HEMLOCK",
+        "LAST",
+};
+
 /*
  * Clear GPU surface registers.
  */
@@ -44,10 +93,11 @@ void radeon_surface_init(struct radeon_device *rdev)
         if (rdev->family < CHIP_R600) {
                 int i;
 
-                for (i = 0; i < 8; i++) {
-                        WREG32(RADEON_SURFACE0_INFO +
-                               i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
-                               0);
+                for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
+                        if (rdev->surface_regs[i].bo)
+                                radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
+                        else
+                                radeon_clear_surface_reg(rdev, i);
                 }
                 /* enable surfaces */
                 WREG32(RADEON_SURFACE_CNTL, 0);
@@ -99,80 +149,103 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
         }
 }
 
-/*
- * MC common functions
+/**
+ * radeon_vram_location - try to find VRAM location
+ * @rdev: radeon device structure holding all necessary informations
+ * @mc: memory controller structure holding memory informations
+ * @base: base address at which to put VRAM
+ *
+ * Function will place try to place VRAM at base address provided
+ * as parameter (which is so far either PCI aperture address or
+ * for IGP TOM base address).
+ *
+ * If there is not enough space to fit the unvisible VRAM in the 32bits
+ * address space then we limit the VRAM size to the aperture.
+ *
+ * If we are using AGP and if the AGP aperture doesn't allow us to have
+ * room for all the VRAM than we restrict the VRAM to the PCI aperture
+ * size and print a warning.
+ *
+ * This function will never fails, worst case are limiting VRAM.
+ *
+ * Note: GTT start, end, size should be initialized before calling this
+ * function on AGP platform.
+ *
+ * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
+ * this shouldn't be a problem as we are using the PCI aperture as a reference.
+ * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
+ * not IGP.
+ *
+ * Note: we use mc_vram_size as on some board we need to program the mc to
+ * cover the whole aperture even if VRAM size is inferior to aperture size
+ * Novell bug 204882 + along with lots of ubuntu ones
+ *
+ * Note: when limiting vram it's safe to overwritte real_vram_size because
+ * we are not in case where real_vram_size is inferior to mc_vram_size (ie
+ * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
+ * ones)
+ *
+ * Note: IGP TOM addr should be the same as the aperture addr, we don't
+ * explicitly check for that thought.
+ *
+ * FIXME: when reducing VRAM size align new size on power of 2.
  */
-int radeon_mc_setup(struct radeon_device *rdev)
+void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
+{
+        mc->vram_start = base;
+        if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
+                dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
+                mc->real_vram_size = mc->aper_size;
+                mc->mc_vram_size = mc->aper_size;
+        }
+        mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
+        if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
+                dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
+                mc->real_vram_size = mc->aper_size;
+                mc->mc_vram_size = mc->aper_size;
+        }
+        mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
+        dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
+                        mc->mc_vram_size >> 20, mc->vram_start,
+                        mc->vram_end, mc->real_vram_size >> 20);
+}
+
+/**
+ * radeon_gtt_location - try to find GTT location
+ * @rdev: radeon device structure holding all necessary informations
+ * @mc: memory controller structure holding memory informations
+ *
+ * Function will place try to place GTT before or after VRAM.
+ *
+ * If GTT size is bigger than space left then we ajust GTT size.
+ * Thus function will never fails.
+ *
+ * FIXME: when reducing GTT size align new size on power of 2.
+ */
+void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 {
-        uint32_t tmp;
+        u64 size_af, size_bf;
 
-        /* Some chips have an "issue" with the memory controller, the
-         * location must be aligned to the size. We just align it down,
-         * too bad if we walk over the top of system memory, we don't
-         * use DMA without a remapped anyway.
-         * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
-         */
-        /* FGLRX seems to setup like this, VRAM a 0, then GART.
-         */
-        /*
-         * Note: from R6xx the address space is 40bits but here we only
-         * use 32bits (still have to see a card which would exhaust 4G
-         * address space).
-         */
-        if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
-                /* vram location was already setup try to put gtt after
-                 * if it fits */
-                tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
-                tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
-                if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
-                        rdev->mc.gtt_location = tmp;
-                } else {
-                        if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
-                                printk(KERN_ERR "[drm] GTT too big to fit "
-                                       "before or after vram location.\n");
-                                return -EINVAL;
-                        }
-                        rdev->mc.gtt_location = 0;
-                }
-        } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
-                /* gtt location was already setup try to put vram before
-                 * if it fits */
-                if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
-                        rdev->mc.vram_location = 0;
-                } else {
-                        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
-                        tmp += (rdev->mc.mc_vram_size - 1);
-                        tmp &= ~(rdev->mc.mc_vram_size - 1);
-                        if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
-                                rdev->mc.vram_location = tmp;
-                        } else {
-                                printk(KERN_ERR "[drm] vram too big to fit "
-                                       "before or after GTT location.\n");
-                                return -EINVAL;
-                        }
+        size_af = 0xFFFFFFFF - mc->vram_end;
+        size_bf = mc->vram_start;
+        if (size_bf > size_af) {
+                if (mc->gtt_size > size_bf) {
+                        dev_warn(rdev->dev, "limiting GTT\n");
+                        mc->gtt_size = size_bf;
                 }
+                mc->gtt_start = mc->vram_start - mc->gtt_size;
         } else {
-                rdev->mc.vram_location = 0;
-                tmp = rdev->mc.mc_vram_size;
-                tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
-                rdev->mc.gtt_location = tmp;
-        }
-        rdev->mc.vram_start = rdev->mc.vram_location;
-        rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-        rdev->mc.gtt_start = rdev->mc.gtt_location;
-        rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
-        DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
-        DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
-                 (unsigned)rdev->mc.vram_location,
-                 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
-        DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
-        DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
-                 (unsigned)rdev->mc.gtt_location,
-                 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
-        return 0;
+                if (mc->gtt_size > size_af) {
+                        dev_warn(rdev->dev, "limiting GTT\n");
+                        mc->gtt_size = size_af;
+                }
+                mc->gtt_start = mc->vram_end + 1;
+        }
+        mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
+        dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
+                        mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 }
 
-
 /*
  * GPU helpers function.
  */
@@ -181,7 +254,16 @@ bool radeon_card_posted(struct radeon_device *rdev)
         uint32_t reg;
 
         /* first check CRTCs */
-        if (ASIC_IS_AVIVO(rdev)) {
+        if (ASIC_IS_DCE4(rdev)) {
+                reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
+                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
+                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
+                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
+                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
+                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+                if (reg & EVERGREEN_CRTC_MASTER_EN)
+                        return true;
+        } else if (ASIC_IS_AVIVO(rdev)) {
                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
                       RREG32(AVIVO_D2CRTC_CONTROL);
                 if (reg & AVIVO_CRTC_EN) {
@@ -208,8 +290,58 @@ bool radeon_card_posted(struct radeon_device *rdev)
 
 }
 
+void radeon_update_bandwidth_info(struct radeon_device *rdev)
+{
+        fixed20_12 a;
+        u32 sclk, mclk;
+
+        if (rdev->flags & RADEON_IS_IGP) {
+                sclk = radeon_get_engine_clock(rdev);
+                mclk = rdev->clock.default_mclk;
+
+                a.full = rfixed_const(100);
+                rdev->pm.sclk.full = rfixed_const(sclk);
+                rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+                rdev->pm.mclk.full = rfixed_const(mclk);
+                rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
+
+                a.full = rfixed_const(16);
+                /* core_bandwidth = sclk(Mhz) * 16 */
+                rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
+        } else {
+                sclk = radeon_get_engine_clock(rdev);
+                mclk = radeon_get_memory_clock(rdev);
+
+                a.full = rfixed_const(100);
+                rdev->pm.sclk.full = rfixed_const(sclk);
+                rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+                rdev->pm.mclk.full = rfixed_const(mclk);
+                rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
+        }
+}
+
+bool radeon_boot_test_post_card(struct radeon_device *rdev)
+{
+        if (radeon_card_posted(rdev))
+                return true;
+
+        if (rdev->bios) {
+                DRM_INFO("GPU not posted. posting now...\n");
+                if (rdev->is_atom_bios)
+                        atom_asic_init(rdev->mode_info.atom_context);
+                else
+                        radeon_combios_asic_init(rdev->ddev);
+                return true;
+        } else {
+                dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
+                return false;
+        }
+}
+
 int radeon_dummy_page_init(struct radeon_device *rdev)
 {
+        if (rdev->dummy_page.page)
+                return 0;
         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
         if (rdev->dummy_page.page == NULL)
                 return -ENOMEM;
@@ -234,167 +366,6 @@ void radeon_dummy_page_fini(struct radeon_device *rdev)
 }
 
 
-/*
- * Registers accessors functions.
- */
-uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
-{
-        DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
-        BUG_ON(1);
-        return 0;
-}
-
-void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
-{
-        DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
-                  reg, v);
-        BUG_ON(1);
-}
-
-void radeon_register_accessor_init(struct radeon_device *rdev)
-{
-        rdev->mc_rreg = &radeon_invalid_rreg;
-        rdev->mc_wreg = &radeon_invalid_wreg;
-        rdev->pll_rreg = &radeon_invalid_rreg;
-        rdev->pll_wreg = &radeon_invalid_wreg;
-        rdev->pciep_rreg = &radeon_invalid_rreg;
-        rdev->pciep_wreg = &radeon_invalid_wreg;
-
-        /* Don't change order as we are overridding accessor. */
-        if (rdev->family < CHIP_RV515) {
-                rdev->pcie_reg_mask = 0xff;
-        } else {
-                rdev->pcie_reg_mask = 0x7ff;
-        }
-        /* FIXME: not sure here */
-        if (rdev->family <= CHIP_R580) {
-                rdev->pll_rreg = &r100_pll_rreg;
-                rdev->pll_wreg = &r100_pll_wreg;
-        }
-        if (rdev->family >= CHIP_R420) {
-                rdev->mc_rreg = &r420_mc_rreg;
-                rdev->mc_wreg = &r420_mc_wreg;
-        }
-        if (rdev->family >= CHIP_RV515) {
-                rdev->mc_rreg = &rv515_mc_rreg;
-                rdev->mc_wreg = &rv515_mc_wreg;
-        }
-        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
-                rdev->mc_rreg = &rs400_mc_rreg;
-                rdev->mc_wreg = &rs400_mc_wreg;
-        }
-        if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
-                rdev->mc_rreg = &rs690_mc_rreg;
-                rdev->mc_wreg = &rs690_mc_wreg;
-        }
-        if (rdev->family == CHIP_RS600) {
-                rdev->mc_rreg = &rs600_mc_rreg;
-                rdev->mc_wreg = &rs600_mc_wreg;
-        }
-        if (rdev->family >= CHIP_R600) {
-                rdev->pciep_rreg = &r600_pciep_rreg;
-                rdev->pciep_wreg = &r600_pciep_wreg;
-        }
-}
-
-
-/*
- * ASIC
- */
-int radeon_asic_init(struct radeon_device *rdev)
-{
-        radeon_register_accessor_init(rdev);
-        switch (rdev->family) {
-        case CHIP_R100:
-        case CHIP_RV100:
-        case CHIP_RS100:
-        case CHIP_RV200:
-        case CHIP_RS200:
-        case CHIP_R200:
-        case CHIP_RV250:
-        case CHIP_RS300:
-        case CHIP_RV280:
-                rdev->asic = &r100_asic;
-                break;
-        case CHIP_R300:
-        case CHIP_R350:
-        case CHIP_RV350:
-        case CHIP_RV380:
-                rdev->asic = &r300_asic;
-                if (rdev->flags & RADEON_IS_PCIE) {
-                        rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
-                        rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
-                }
-                break;
-        case CHIP_R420:
-        case CHIP_R423:
-        case CHIP_RV410:
-                rdev->asic = &r420_asic;
-                break;
-        case CHIP_RS400:
-        case CHIP_RS480:
-                rdev->asic = &rs400_asic;
-                break;
-        case CHIP_RS600:
-                rdev->asic = &rs600_asic;
-                break;
-        case CHIP_RS690:
-        case CHIP_RS740:
-                rdev->asic = &rs690_asic;
-                break;
-        case CHIP_RV515:
-                rdev->asic = &rv515_asic;
-                break;
-        case CHIP_R520:
-        case CHIP_RV530:
-        case CHIP_RV560:
-        case CHIP_RV570:
-        case CHIP_R580:
-                rdev->asic = &r520_asic;
-                break;
-        case CHIP_R600:
-        case CHIP_RV610:
-        case CHIP_RV630:
-        case CHIP_RV620:
-        case CHIP_RV635:
-        case CHIP_RV670:
-        case CHIP_RS780:
-        case CHIP_RS880:
-                rdev->asic = &r600_asic;
-                break;
-        case CHIP_RV770:
-        case CHIP_RV730:
-        case CHIP_RV710:
-        case CHIP_RV740:
-                rdev->asic = &rv770_asic;
-                break;
-        default:
-                /* FIXME: not supported yet */
-                return -EINVAL;
-        }
-        return 0;
-}
-
-
-/*
- * Wrapper around modesetting bits.
- */
-int radeon_clocks_init(struct radeon_device *rdev)
-{
-        int r;
-
-        r = radeon_static_clocks_init(rdev->ddev);
-        if (r) {
-                return r;
-        }
-        DRM_INFO("Clocks initialized !\n");
-        return 0;
-}
-
-void radeon_clocks_fini(struct radeon_device *rdev)
-{
-}
-
 /* ATOM accessor methods */
 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 {
@@ -462,13 +433,18 @@ int radeon_atombios_init(struct radeon_device *rdev)
         atom_card_info->pll_write = cail_pll_write;
 
         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
+        mutex_init(&rdev->mode_info.atom_context->mutex);
         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
+        atom_allocate_fb_scratch(rdev->mode_info.atom_context);
         return 0;
 }
 
 void radeon_atombios_fini(struct radeon_device *rdev)
 {
-        kfree(rdev->mode_info.atom_context);
+        if (rdev->mode_info.atom_context) {
+                kfree(rdev->mode_info.atom_context->scratch);
+                kfree(rdev->mode_info.atom_context);
+        }
         kfree(rdev->mode_info.atom_card_info);
 }
 
@@ -494,31 +470,102 @@ static unsigned int radeon_vga_set_decode(void *cookie, bool state)
                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 }
 
-void radeon_agp_disable(struct radeon_device *rdev)
-{
-        rdev->flags &= ~RADEON_IS_AGP;
-        if (rdev->family >= CHIP_R600) {
-                DRM_INFO("Forcing AGP to PCIE mode\n");
-                rdev->flags |= RADEON_IS_PCIE;
-        } else if (rdev->family >= CHIP_RV515 ||
-                        rdev->family == CHIP_RV380 ||
-                        rdev->family == CHIP_RV410 ||
-                        rdev->family == CHIP_R423) {
-                DRM_INFO("Forcing AGP to PCIE mode\n");
-                rdev->flags |= RADEON_IS_PCIE;
-                rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
-                rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+void radeon_check_arguments(struct radeon_device *rdev)
+{
+        /* vramlimit must be a power of two */
+        switch (radeon_vram_limit) {
+        case 0:
+        case 4:
+        case 8:
+        case 16:
+        case 32:
+        case 64:
+        case 128:
+        case 256:
+        case 512:
+        case 1024:
+        case 2048:
+        case 4096:
+                break;
+        default:
+                dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
+                                radeon_vram_limit);
+                radeon_vram_limit = 0;
+                break;
+        }
+        radeon_vram_limit = radeon_vram_limit << 20;
+        /* gtt size must be power of two and greater or equal to 32M */
+        switch (radeon_gart_size) {
+        case 4:
+        case 8:
+        case 16:
+                dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
+                                radeon_gart_size);
+                radeon_gart_size = 512;
+                break;
+        case 32:
+        case 64:
+        case 128:
+        case 256:
+        case 512:
+        case 1024:
+        case 2048:
+        case 4096:
+                break;
+        default:
+                dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
+                                radeon_gart_size);
+                radeon_gart_size = 512;
+                break;
+        }
+        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+        /* AGP mode can only be -1, 1, 2, 4, 8 */
+        switch (radeon_agpmode) {
+        case -1:
+        case 0:
+        case 1:
+        case 2:
+        case 4:
+        case 8:
+                break;
+        default:
+                dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
+                                "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
+                radeon_agpmode = 0;
+                break;
+        }
+}
+
+static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
+{
+        struct drm_device *dev = pci_get_drvdata(pdev);
+        struct radeon_device *rdev = dev->dev_private;
+        pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
+        if (state == VGA_SWITCHEROO_ON) {
+                printk(KERN_INFO "radeon: switched on\n");
+                /* don't suspend or resume card normally */
+                rdev->powered_down = false;
+                radeon_resume_kms(dev);
         } else {
-                DRM_INFO("Forcing AGP to PCI mode\n");
-                rdev->flags |= RADEON_IS_PCI;
-                rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
-                rdev->asic->gart_set_page = &r100_pci_gart_set_page;
+                printk(KERN_INFO "radeon: switched off\n");
+                radeon_suspend_kms(dev, pmm);
+                /* don't suspend or resume card normally */
+                rdev->powered_down = true;
         }
 }
 
-/*
- * Radeon device.
- */
+static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
+{
+        struct drm_device *dev = pci_get_drvdata(pdev);
+        bool can_switch;
+
+        spin_lock(&dev->count_lock);
+        can_switch = (dev->open_count == 0);
+        spin_unlock(&dev->count_lock);
+        return can_switch;
+}
+
+
 int radeon_device_init(struct radeon_device *rdev,
                        struct drm_device *ddev,
                        struct pci_dev *pdev,
@@ -527,7 +574,6 @@ int radeon_device_init(struct radeon_device *rdev,
         int r;
         int dma_bits;
 
-        DRM_INFO("radeon: Initializing kernel modesetting.\n");
         rdev->shutdown = false;
         rdev->dev = &pdev->dev;
         rdev->ddev = ddev;
@@ -539,21 +585,44 @@ int radeon_device_init(struct radeon_device *rdev,
         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
         rdev->gpu_lockup = false;
         rdev->accel_working = false;
+
+        DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
+                radeon_family_name[rdev->family], pdev->vendor, pdev->device);
+
         /* mutex initialization are all done here so we
          * can recall function without having locking issues */
         mutex_init(&rdev->cs_mutex);
         mutex_init(&rdev->ib_pool.mutex);
         mutex_init(&rdev->cp.mutex);
+        mutex_init(&rdev->dc_hw_i2c_mutex);
+        if (rdev->family >= CHIP_R600)
+                spin_lock_init(&rdev->ih.lock);
+        mutex_init(&rdev->gem.mutex);
+        mutex_init(&rdev->pm.mutex);
         rwlock_init(&rdev->fence_drv.lock);
         INIT_LIST_HEAD(&rdev->gem.objects);
+        init_waitqueue_head(&rdev->irq.vblank_queue);
+
+        /* setup workqueue */
+        rdev->wq = create_workqueue("radeon");
+        if (rdev->wq == NULL)
+                return -ENOMEM;
 
         /* Set asic functions */
         r = radeon_asic_init(rdev);
-        if (r) {
+        if (r)
                 return r;
+        radeon_check_arguments(rdev);
+
+        /* all of the newer IGP chips have an internal gart
+         * However some rs4xx report as AGP, so remove that here.
+         */
+        if ((rdev->family >= CHIP_RS400) &&
+            (rdev->flags & RADEON_IS_IGP)) {
+                rdev->flags &= ~RADEON_IS_AGP;
         }
 
-        if (radeon_agpmode == -1) {
+        if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
                 radeon_agp_disable(rdev);
         }
 
@@ -590,6 +659,9 @@ int radeon_device_init(struct radeon_device *rdev,
         /* this will fail for cards that aren't VGA class devices, just
          * ignore it */
         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
+        vga_switcheroo_register_client(rdev->pdev,
+                                       radeon_switcheroo_set_state,
+                                       radeon_switcheroo_can_switch);
 
         r = radeon_init(rdev);
         if (r)
@@ -620,6 +692,8 @@ void radeon_device_fini(struct radeon_device *rdev)
         DRM_INFO("radeon: finishing device.\n");
         rdev->shutdown = true;
         radeon_fini(rdev);
+        destroy_workqueue(rdev->wq);
+        vga_switcheroo_unregister_client(rdev->pdev);
         vga_client_register(rdev->pdev, NULL, NULL, NULL);
         iounmap(rdev->rmmio);
         rdev->rmmio = NULL;
@@ -631,38 +705,48 @@ void radeon_device_fini(struct radeon_device *rdev)
  */
 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 {
-        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_device *rdev;
         struct drm_crtc *crtc;
+        int r;
 
-        if (dev == NULL || rdev == NULL) {
+        if (dev == NULL || dev->dev_private == NULL) {
                 return -ENODEV;
         }
         if (state.event == PM_EVENT_PRETHAW) {
                 return 0;
         }
+        rdev = dev->dev_private;
+
+        if (rdev->powered_down)
+                return 0;
         /* unpin the front buffers */
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
-                struct radeon_object *robj;
+                struct radeon_bo *robj;
 
                 if (rfb == NULL || rfb->obj == NULL) {
                         continue;
                 }
                 robj = rfb->obj->driver_private;
-                if (robj != rdev->fbdev_robj) {
-                        radeon_object_unpin(robj);
+                if (robj != rdev->fbdev_rbo) {
+                        r = radeon_bo_reserve(robj, false);
+                        if (unlikely(r == 0)) {
+                                radeon_bo_unpin(robj);
+                                radeon_bo_unreserve(robj);
+                        }
                 }
         }
         /* evict vram memory */
-        radeon_object_evict_vram(rdev);
+        radeon_bo_evict_vram(rdev);
         /* wait for gpu to finish processing current batch */
         radeon_fence_wait_last(rdev);
 
         radeon_save_bios_scratch_regs(rdev);
 
         radeon_suspend(rdev);
+        radeon_hpd_fini(rdev);
         /* evict remaining vram memory */
-        radeon_object_evict_vram(rdev);
+        radeon_bo_evict_vram(rdev);
 
         pci_save_state(dev->pdev);
         if (state.event == PM_EVENT_SUSPEND) {
@@ -680,6 +764,9 @@ int radeon_resume_kms(struct drm_device *dev)
 {
         struct radeon_device *rdev = dev->dev_private;
 
+        if (rdev->powered_down)
+                return 0;
+
         acquire_console_sem();
         pci_set_power_state(dev->pdev, PCI_D0);
         pci_restore_state(dev->pdev);
@@ -695,6 +782,8 @@ int radeon_resume_kms(struct drm_device *dev)
         fb_set_suspend(rdev->fbdev_info, 0);
         release_console_sem();
 
+        /* reset hpd state */
+        radeon_hpd_init(rdev);
         /* blat the mode back in */
         drm_helper_resume_force_mode(dev);
         return 0;