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authorAlex Deucher <alexander.deucher@amd.com>2012-02-23 17:53:46 -0500
committerDave Airlie <airlied@redhat.com>2012-02-29 05:14:57 -0500
commitc5b3b8504f17003ff9cd94ff4b385a6144410b25 (patch)
tree24730517cdb7cb25f59acd144798e7b0f80d1f90 /drivers/gpu/drm/radeon/radeon_asic.c
parentf712812e1ba7f17a270f285c3e7e70c65186a8b4 (diff)
drm/radeon/kms: reorganize gart callbacks
tidy up the radeon_asic struct. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c110
1 files changed, 72 insertions, 38 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 85e13502e80f..1fd6e56cafe9 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -114,13 +114,13 @@ void radeon_agp_disable(struct radeon_device *rdev)
114 rdev->family == CHIP_R423) { 114 rdev->family == CHIP_R423) {
115 DRM_INFO("Forcing AGP to PCIE mode\n"); 115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev->flags |= RADEON_IS_PCIE; 116 rdev->flags |= RADEON_IS_PCIE;
117 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 117 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
118 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 118 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
119 } else { 119 } else {
120 DRM_INFO("Forcing AGP to PCI mode\n"); 120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev->flags |= RADEON_IS_PCI; 121 rdev->flags |= RADEON_IS_PCI;
122 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 122 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
123 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 123 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
124 } 124 }
125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126} 126}
@@ -136,8 +136,10 @@ static struct radeon_asic r100_asic = {
136 .vga_set_state = &r100_vga_set_state, 136 .vga_set_state = &r100_vga_set_state,
137 .gpu_is_lockup = &r100_gpu_is_lockup, 137 .gpu_is_lockup = &r100_gpu_is_lockup,
138 .asic_reset = &r100_asic_reset, 138 .asic_reset = &r100_asic_reset,
139 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 139 .gart = {
140 .gart_set_page = &r100_pci_gart_set_page, 140 .tlb_flush = &r100_pci_gart_tlb_flush,
141 .set_page = &r100_pci_gart_set_page,
142 },
141 .ring = { 143 .ring = {
142 [RADEON_RING_TYPE_GFX_INDEX] = { 144 [RADEON_RING_TYPE_GFX_INDEX] = {
143 .ib_execute = &r100_ring_ib_execute, 145 .ib_execute = &r100_ring_ib_execute,
@@ -204,8 +206,10 @@ static struct radeon_asic r200_asic = {
204 .vga_set_state = &r100_vga_set_state, 206 .vga_set_state = &r100_vga_set_state,
205 .gpu_is_lockup = &r100_gpu_is_lockup, 207 .gpu_is_lockup = &r100_gpu_is_lockup,
206 .asic_reset = &r100_asic_reset, 208 .asic_reset = &r100_asic_reset,
207 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 209 .gart = {
208 .gart_set_page = &r100_pci_gart_set_page, 210 .tlb_flush = &r100_pci_gart_tlb_flush,
211 .set_page = &r100_pci_gart_set_page,
212 },
209 .ring = { 213 .ring = {
210 [RADEON_RING_TYPE_GFX_INDEX] = { 214 [RADEON_RING_TYPE_GFX_INDEX] = {
211 .ib_execute = &r100_ring_ib_execute, 215 .ib_execute = &r100_ring_ib_execute,
@@ -271,8 +275,10 @@ static struct radeon_asic r300_asic = {
271 .vga_set_state = &r100_vga_set_state, 275 .vga_set_state = &r100_vga_set_state,
272 .gpu_is_lockup = &r300_gpu_is_lockup, 276 .gpu_is_lockup = &r300_gpu_is_lockup,
273 .asic_reset = &r300_asic_reset, 277 .asic_reset = &r300_asic_reset,
274 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 278 .gart = {
275 .gart_set_page = &r100_pci_gart_set_page, 279 .tlb_flush = &r100_pci_gart_tlb_flush,
280 .set_page = &r100_pci_gart_set_page,
281 },
276 .ring = { 282 .ring = {
277 [RADEON_RING_TYPE_GFX_INDEX] = { 283 [RADEON_RING_TYPE_GFX_INDEX] = {
278 .ib_execute = &r100_ring_ib_execute, 284 .ib_execute = &r100_ring_ib_execute,
@@ -339,8 +345,10 @@ static struct radeon_asic r300_asic_pcie = {
339 .vga_set_state = &r100_vga_set_state, 345 .vga_set_state = &r100_vga_set_state,
340 .gpu_is_lockup = &r300_gpu_is_lockup, 346 .gpu_is_lockup = &r300_gpu_is_lockup,
341 .asic_reset = &r300_asic_reset, 347 .asic_reset = &r300_asic_reset,
342 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 348 .gart = {
343 .gart_set_page = &rv370_pcie_gart_set_page, 349 .tlb_flush = &rv370_pcie_gart_tlb_flush,
350 .set_page = &rv370_pcie_gart_set_page,
351 },
344 .ring = { 352 .ring = {
345 [RADEON_RING_TYPE_GFX_INDEX] = { 353 [RADEON_RING_TYPE_GFX_INDEX] = {
346 .ib_execute = &r100_ring_ib_execute, 354 .ib_execute = &r100_ring_ib_execute,
@@ -406,8 +414,10 @@ static struct radeon_asic r420_asic = {
406 .vga_set_state = &r100_vga_set_state, 414 .vga_set_state = &r100_vga_set_state,
407 .gpu_is_lockup = &r300_gpu_is_lockup, 415 .gpu_is_lockup = &r300_gpu_is_lockup,
408 .asic_reset = &r300_asic_reset, 416 .asic_reset = &r300_asic_reset,
409 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 417 .gart = {
410 .gart_set_page = &rv370_pcie_gart_set_page, 418 .tlb_flush = &rv370_pcie_gart_tlb_flush,
419 .set_page = &rv370_pcie_gart_set_page,
420 },
411 .ring = { 421 .ring = {
412 [RADEON_RING_TYPE_GFX_INDEX] = { 422 [RADEON_RING_TYPE_GFX_INDEX] = {
413 .ib_execute = &r100_ring_ib_execute, 423 .ib_execute = &r100_ring_ib_execute,
@@ -474,8 +484,10 @@ static struct radeon_asic rs400_asic = {
474 .vga_set_state = &r100_vga_set_state, 484 .vga_set_state = &r100_vga_set_state,
475 .gpu_is_lockup = &r300_gpu_is_lockup, 485 .gpu_is_lockup = &r300_gpu_is_lockup,
476 .asic_reset = &r300_asic_reset, 486 .asic_reset = &r300_asic_reset,
477 .gart_tlb_flush = &rs400_gart_tlb_flush, 487 .gart = {
478 .gart_set_page = &rs400_gart_set_page, 488 .tlb_flush = &rs400_gart_tlb_flush,
489 .set_page = &rs400_gart_set_page,
490 },
479 .ring = { 491 .ring = {
480 [RADEON_RING_TYPE_GFX_INDEX] = { 492 [RADEON_RING_TYPE_GFX_INDEX] = {
481 .ib_execute = &r100_ring_ib_execute, 493 .ib_execute = &r100_ring_ib_execute,
@@ -542,8 +554,10 @@ static struct radeon_asic rs600_asic = {
542 .vga_set_state = &r100_vga_set_state, 554 .vga_set_state = &r100_vga_set_state,
543 .gpu_is_lockup = &r300_gpu_is_lockup, 555 .gpu_is_lockup = &r300_gpu_is_lockup,
544 .asic_reset = &rs600_asic_reset, 556 .asic_reset = &rs600_asic_reset,
545 .gart_tlb_flush = &rs600_gart_tlb_flush, 557 .gart = {
546 .gart_set_page = &rs600_gart_set_page, 558 .tlb_flush = &rs600_gart_tlb_flush,
559 .set_page = &rs600_gart_set_page,
560 },
547 .ring = { 561 .ring = {
548 [RADEON_RING_TYPE_GFX_INDEX] = { 562 [RADEON_RING_TYPE_GFX_INDEX] = {
549 .ib_execute = &r100_ring_ib_execute, 563 .ib_execute = &r100_ring_ib_execute,
@@ -610,8 +624,10 @@ static struct radeon_asic rs690_asic = {
610 .vga_set_state = &r100_vga_set_state, 624 .vga_set_state = &r100_vga_set_state,
611 .gpu_is_lockup = &r300_gpu_is_lockup, 625 .gpu_is_lockup = &r300_gpu_is_lockup,
612 .asic_reset = &rs600_asic_reset, 626 .asic_reset = &rs600_asic_reset,
613 .gart_tlb_flush = &rs400_gart_tlb_flush, 627 .gart = {
614 .gart_set_page = &rs400_gart_set_page, 628 .tlb_flush = &rs400_gart_tlb_flush,
629 .set_page = &rs400_gart_set_page,
630 },
615 .ring = { 631 .ring = {
616 [RADEON_RING_TYPE_GFX_INDEX] = { 632 [RADEON_RING_TYPE_GFX_INDEX] = {
617 .ib_execute = &r100_ring_ib_execute, 633 .ib_execute = &r100_ring_ib_execute,
@@ -678,8 +694,10 @@ static struct radeon_asic rv515_asic = {
678 .vga_set_state = &r100_vga_set_state, 694 .vga_set_state = &r100_vga_set_state,
679 .gpu_is_lockup = &r300_gpu_is_lockup, 695 .gpu_is_lockup = &r300_gpu_is_lockup,
680 .asic_reset = &rs600_asic_reset, 696 .asic_reset = &rs600_asic_reset,
681 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 697 .gart = {
682 .gart_set_page = &rv370_pcie_gart_set_page, 698 .tlb_flush = &rv370_pcie_gart_tlb_flush,
699 .set_page = &rv370_pcie_gart_set_page,
700 },
683 .ring = { 701 .ring = {
684 [RADEON_RING_TYPE_GFX_INDEX] = { 702 [RADEON_RING_TYPE_GFX_INDEX] = {
685 .ib_execute = &r100_ring_ib_execute, 703 .ib_execute = &r100_ring_ib_execute,
@@ -746,8 +764,10 @@ static struct radeon_asic r520_asic = {
746 .vga_set_state = &r100_vga_set_state, 764 .vga_set_state = &r100_vga_set_state,
747 .gpu_is_lockup = &r300_gpu_is_lockup, 765 .gpu_is_lockup = &r300_gpu_is_lockup,
748 .asic_reset = &rs600_asic_reset, 766 .asic_reset = &rs600_asic_reset,
749 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 767 .gart = {
750 .gart_set_page = &rv370_pcie_gart_set_page, 768 .tlb_flush = &rv370_pcie_gart_tlb_flush,
769 .set_page = &rv370_pcie_gart_set_page,
770 },
751 .ring = { 771 .ring = {
752 [RADEON_RING_TYPE_GFX_INDEX] = { 772 [RADEON_RING_TYPE_GFX_INDEX] = {
753 .ib_execute = &r100_ring_ib_execute, 773 .ib_execute = &r100_ring_ib_execute,
@@ -814,8 +834,10 @@ static struct radeon_asic r600_asic = {
814 .vga_set_state = &r600_vga_set_state, 834 .vga_set_state = &r600_vga_set_state,
815 .gpu_is_lockup = &r600_gpu_is_lockup, 835 .gpu_is_lockup = &r600_gpu_is_lockup,
816 .asic_reset = &r600_asic_reset, 836 .asic_reset = &r600_asic_reset,
817 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 837 .gart = {
818 .gart_set_page = &rs600_gart_set_page, 838 .tlb_flush = &r600_pcie_gart_tlb_flush,
839 .set_page = &rs600_gart_set_page,
840 },
819 .ring = { 841 .ring = {
820 [RADEON_RING_TYPE_GFX_INDEX] = { 842 [RADEON_RING_TYPE_GFX_INDEX] = {
821 .ib_execute = &r600_ring_ib_execute, 843 .ib_execute = &r600_ring_ib_execute,
@@ -881,8 +903,10 @@ static struct radeon_asic rs780_asic = {
881 .gpu_is_lockup = &r600_gpu_is_lockup, 903 .gpu_is_lockup = &r600_gpu_is_lockup,
882 .vga_set_state = &r600_vga_set_state, 904 .vga_set_state = &r600_vga_set_state,
883 .asic_reset = &r600_asic_reset, 905 .asic_reset = &r600_asic_reset,
884 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 906 .gart = {
885 .gart_set_page = &rs600_gart_set_page, 907 .tlb_flush = &r600_pcie_gart_tlb_flush,
908 .set_page = &rs600_gart_set_page,
909 },
886 .ring = { 910 .ring = {
887 [RADEON_RING_TYPE_GFX_INDEX] = { 911 [RADEON_RING_TYPE_GFX_INDEX] = {
888 .ib_execute = &r600_ring_ib_execute, 912 .ib_execute = &r600_ring_ib_execute,
@@ -948,8 +972,10 @@ static struct radeon_asic rv770_asic = {
948 .asic_reset = &r600_asic_reset, 972 .asic_reset = &r600_asic_reset,
949 .gpu_is_lockup = &r600_gpu_is_lockup, 973 .gpu_is_lockup = &r600_gpu_is_lockup,
950 .vga_set_state = &r600_vga_set_state, 974 .vga_set_state = &r600_vga_set_state,
951 .gart_tlb_flush = &r600_pcie_gart_tlb_flush, 975 .gart = {
952 .gart_set_page = &rs600_gart_set_page, 976 .tlb_flush = &r600_pcie_gart_tlb_flush,
977 .set_page = &rs600_gart_set_page,
978 },
953 .ring = { 979 .ring = {
954 [RADEON_RING_TYPE_GFX_INDEX] = { 980 [RADEON_RING_TYPE_GFX_INDEX] = {
955 .ib_execute = &r600_ring_ib_execute, 981 .ib_execute = &r600_ring_ib_execute,
@@ -1015,8 +1041,10 @@ static struct radeon_asic evergreen_asic = {
1015 .gpu_is_lockup = &evergreen_gpu_is_lockup, 1041 .gpu_is_lockup = &evergreen_gpu_is_lockup,
1016 .asic_reset = &evergreen_asic_reset, 1042 .asic_reset = &evergreen_asic_reset,
1017 .vga_set_state = &r600_vga_set_state, 1043 .vga_set_state = &r600_vga_set_state,
1018 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 1044 .gart = {
1019 .gart_set_page = &rs600_gart_set_page, 1045 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1046 .set_page = &rs600_gart_set_page,
1047 },
1020 .ring = { 1048 .ring = {
1021 [RADEON_RING_TYPE_GFX_INDEX] = { 1049 [RADEON_RING_TYPE_GFX_INDEX] = {
1022 .ib_execute = &evergreen_ring_ib_execute, 1050 .ib_execute = &evergreen_ring_ib_execute,
@@ -1082,8 +1110,10 @@ static struct radeon_asic sumo_asic = {
1082 .gpu_is_lockup = &evergreen_gpu_is_lockup, 1110 .gpu_is_lockup = &evergreen_gpu_is_lockup,
1083 .asic_reset = &evergreen_asic_reset, 1111 .asic_reset = &evergreen_asic_reset,
1084 .vga_set_state = &r600_vga_set_state, 1112 .vga_set_state = &r600_vga_set_state,
1085 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 1113 .gart = {
1086 .gart_set_page = &rs600_gart_set_page, 1114 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1115 .set_page = &rs600_gart_set_page,
1116 },
1087 .ring = { 1117 .ring = {
1088 [RADEON_RING_TYPE_GFX_INDEX] = { 1118 [RADEON_RING_TYPE_GFX_INDEX] = {
1089 .ib_execute = &evergreen_ring_ib_execute, 1119 .ib_execute = &evergreen_ring_ib_execute,
@@ -1149,8 +1179,10 @@ static struct radeon_asic btc_asic = {
1149 .gpu_is_lockup = &evergreen_gpu_is_lockup, 1179 .gpu_is_lockup = &evergreen_gpu_is_lockup,
1150 .asic_reset = &evergreen_asic_reset, 1180 .asic_reset = &evergreen_asic_reset,
1151 .vga_set_state = &r600_vga_set_state, 1181 .vga_set_state = &r600_vga_set_state,
1152 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, 1182 .gart = {
1153 .gart_set_page = &rs600_gart_set_page, 1183 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1184 .set_page = &rs600_gart_set_page,
1185 },
1154 .ring = { 1186 .ring = {
1155 [RADEON_RING_TYPE_GFX_INDEX] = { 1187 [RADEON_RING_TYPE_GFX_INDEX] = {
1156 .ib_execute = &evergreen_ring_ib_execute, 1188 .ib_execute = &evergreen_ring_ib_execute,
@@ -1226,8 +1258,10 @@ static struct radeon_asic cayman_asic = {
1226 .gpu_is_lockup = &cayman_gpu_is_lockup, 1258 .gpu_is_lockup = &cayman_gpu_is_lockup,
1227 .asic_reset = &cayman_asic_reset, 1259 .asic_reset = &cayman_asic_reset,
1228 .vga_set_state = &r600_vga_set_state, 1260 .vga_set_state = &r600_vga_set_state,
1229 .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, 1261 .gart = {
1230 .gart_set_page = &rs600_gart_set_page, 1262 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1263 .set_page = &rs600_gart_set_page,
1264 },
1231 .ring = { 1265 .ring = {
1232 [RADEON_RING_TYPE_GFX_INDEX] = { 1266 [RADEON_RING_TYPE_GFX_INDEX] = {
1233 .ib_execute = &cayman_ring_ib_execute, 1267 .ib_execute = &cayman_ring_ib_execute,