diff options
author | Christian König <christian.koenig@amd.com> | 2013-04-16 16:11:22 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-08-27 12:47:55 -0400 |
commit | 856754c3a23a622d26a82b29fab6429481705511 (patch) | |
tree | db28167b75af368213784b89c35804f62d6bf16c /drivers/gpu/drm/radeon/radeon_asic.c | |
parent | 4a956a70a8d4cc5268a60f6718de58892fa1275e (diff) |
drm/radeon: add UVD support for older asics v4
v2: cleanup R600 support
v3: rebased on current drm-fixes-3.12
v4: rebased on drm-next-3.14
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index eeeeabe09758..9e6699a9a0b4 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -965,6 +965,19 @@ static struct radeon_asic r600_asic = { | |||
965 | }, | 965 | }, |
966 | }; | 966 | }; |
967 | 967 | ||
968 | static struct radeon_asic_ring rv6xx_uvd_ring = { | ||
969 | .ib_execute = &uvd_v1_0_ib_execute, | ||
970 | .emit_fence = &uvd_v1_0_fence_emit, | ||
971 | .emit_semaphore = &uvd_v1_0_semaphore_emit, | ||
972 | .cs_parse = &radeon_uvd_cs_parse, | ||
973 | .ring_test = &uvd_v1_0_ring_test, | ||
974 | .ib_test = &uvd_v1_0_ib_test, | ||
975 | .is_lockup = &radeon_ring_test_lockup, | ||
976 | .get_rptr = &uvd_v1_0_get_rptr, | ||
977 | .get_wptr = &uvd_v1_0_get_wptr, | ||
978 | .set_wptr = &uvd_v1_0_set_wptr, | ||
979 | }; | ||
980 | |||
968 | static struct radeon_asic rv6xx_asic = { | 981 | static struct radeon_asic rv6xx_asic = { |
969 | .init = &r600_init, | 982 | .init = &r600_init, |
970 | .fini = &r600_fini, | 983 | .fini = &r600_fini, |
@@ -984,6 +997,7 @@ static struct radeon_asic rv6xx_asic = { | |||
984 | .ring = { | 997 | .ring = { |
985 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, | 998 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
986 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | 999 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, |
1000 | [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, | ||
987 | }, | 1001 | }, |
988 | .irq = { | 1002 | .irq = { |
989 | .set = &r600_irq_set, | 1003 | .set = &r600_irq_set, |
@@ -1074,6 +1088,7 @@ static struct radeon_asic rs780_asic = { | |||
1074 | .ring = { | 1088 | .ring = { |
1075 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, | 1089 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1076 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | 1090 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, |
1091 | [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, | ||
1077 | }, | 1092 | }, |
1078 | .irq = { | 1093 | .irq = { |
1079 | .set = &r600_irq_set, | 1094 | .set = &r600_irq_set, |