drm/radeon: clean up vram/gtt location handling

Add a per-asic MC (memory controller) mask which holds the
mak address mask the asic is capable of.  Use this when
calculating the vram and gtt locations rather using asic
specific functions or limiting everything to 32 bits.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8263af3fd832..8bd875304441 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -517,6 +517,7 @@ struct radeon_mc {
         bool                    vram_is_ddr;
         bool                    igp_sideport_enabled;
         u64                     gtt_base_align;
+        u64                     mc_mask;
 };
 
 bool radeon_combios_sideport_present(struct radeon_device *rdev);