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authorJ. Bruce Fields <bfields@citi.umich.edu>2010-03-04 12:03:16 -0500
committerJ. Bruce Fields <bfields@citi.umich.edu>2010-03-04 12:04:51 -0500
commit4ea41e2de5bba756858bb40f964e3490b6d1a25c (patch)
tree51a688be321dd42f80d8a0c966eb6a60408d50b3 /drivers/gpu/drm/radeon/radeon.h
parent8d75da8afd068fa58b35e69c7c8c46770d9e7a98 (diff)
parent398007f863a4af2b4a5a07219c5a617f1a098115 (diff)
Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs into for-2.6.34-incoming
Resolve merge conflict in fs/xfs/linux-2.6/xfs_export.c.
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h29
1 files changed, 21 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index eb5f99b9469d..c0356bb193e5 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -96,6 +96,7 @@ extern int radeon_audio;
96 * symbol; 96 * symbol;
97 */ 97 */
98#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 98#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
99/* RADEON_IB_POOL_SIZE must be a power of 2 */
99#define RADEON_IB_POOL_SIZE 16 100#define RADEON_IB_POOL_SIZE 16
100#define RADEON_DEBUGFS_MAX_NUM_FILES 32 101#define RADEON_DEBUGFS_MAX_NUM_FILES 32
101#define RADEONFB_CONN_LIMIT 4 102#define RADEONFB_CONN_LIMIT 4
@@ -363,11 +364,12 @@ void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
363 */ 364 */
364struct radeon_ib { 365struct radeon_ib {
365 struct list_head list; 366 struct list_head list;
366 unsigned long idx; 367 unsigned idx;
367 uint64_t gpu_addr; 368 uint64_t gpu_addr;
368 struct radeon_fence *fence; 369 struct radeon_fence *fence;
369 uint32_t *ptr; 370 uint32_t *ptr;
370 uint32_t length_dw; 371 uint32_t length_dw;
372 bool free;
371}; 373};
372 374
373/* 375/*
@@ -377,10 +379,9 @@ struct radeon_ib {
377struct radeon_ib_pool { 379struct radeon_ib_pool {
378 struct mutex mutex; 380 struct mutex mutex;
379 struct radeon_bo *robj; 381 struct radeon_bo *robj;
380 struct list_head scheduled_ibs;
381 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 382 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
382 bool ready; 383 bool ready;
383 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); 384 unsigned head_id;
384}; 385};
385 386
386struct radeon_cp { 387struct radeon_cp {
@@ -410,13 +411,13 @@ struct r600_ih {
410 unsigned wptr_old; 411 unsigned wptr_old;
411 unsigned ring_size; 412 unsigned ring_size;
412 uint64_t gpu_addr; 413 uint64_t gpu_addr;
413 uint32_t align_mask;
414 uint32_t ptr_mask; 414 uint32_t ptr_mask;
415 spinlock_t lock; 415 spinlock_t lock;
416 bool enabled; 416 bool enabled;
417}; 417};
418 418
419struct r600_blit { 419struct r600_blit {
420 struct mutex mutex;
420 struct radeon_bo *shader_obj; 421 struct radeon_bo *shader_obj;
421 u64 shader_gpu_addr; 422 u64 shader_gpu_addr;
422 u32 vs_offset, ps_offset; 423 u32 vs_offset, ps_offset;
@@ -465,6 +466,7 @@ struct radeon_cs_chunk {
465}; 466};
466 467
467struct radeon_cs_parser { 468struct radeon_cs_parser {
469 struct device *dev;
468 struct radeon_device *rdev; 470 struct radeon_device *rdev;
469 struct drm_file *filp; 471 struct drm_file *filp;
470 /* chunks */ 472 /* chunks */
@@ -660,6 +662,13 @@ struct radeon_asic {
660 void (*hpd_fini)(struct radeon_device *rdev); 662 void (*hpd_fini)(struct radeon_device *rdev);
661 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 663 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
662 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 664 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
665 /* ioctl hw specific callback. Some hw might want to perform special
666 * operation on specific ioctl. For instance on wait idle some hw
667 * might want to perform and HDP flush through MMIO as it seems that
668 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
669 * through ring.
670 */
671 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
663}; 672};
664 673
665/* 674/*
@@ -847,7 +856,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
847 856
848static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 857static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
849{ 858{
850 if (reg < 0x10000) 859 if (reg < rdev->rmmio_size)
851 return readl(((void __iomem *)rdev->rmmio) + reg); 860 return readl(((void __iomem *)rdev->rmmio) + reg);
852 else { 861 else {
853 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 862 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -857,7 +866,7 @@ static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
857 866
858static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 867static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
859{ 868{
860 if (reg < 0x10000) 869 if (reg < rdev->rmmio_size)
861 writel(v, ((void __iomem *)rdev->rmmio) + reg); 870 writel(v, ((void __iomem *)rdev->rmmio) + reg);
862 else { 871 else {
863 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 872 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -1017,6 +1026,8 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1017#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1026#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1018 1027
1019/* Common functions */ 1028/* Common functions */
1029/* AGP */
1030extern void radeon_agp_disable(struct radeon_device *rdev);
1020extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1031extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1021extern int radeon_modeset_init(struct radeon_device *rdev); 1032extern int radeon_modeset_init(struct radeon_device *rdev);
1022extern void radeon_modeset_fini(struct radeon_device *rdev); 1033extern void radeon_modeset_fini(struct radeon_device *rdev);
@@ -1140,6 +1151,7 @@ extern bool r600_card_posted(struct radeon_device *rdev);
1140extern void r600_cp_stop(struct radeon_device *rdev); 1151extern void r600_cp_stop(struct radeon_device *rdev);
1141extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1152extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1142extern int r600_cp_resume(struct radeon_device *rdev); 1153extern int r600_cp_resume(struct radeon_device *rdev);
1154extern void r600_cp_fini(struct radeon_device *rdev);
1143extern int r600_count_pipe_bits(uint32_t val); 1155extern int r600_count_pipe_bits(uint32_t val);
1144extern int r600_gart_clear_page(struct radeon_device *rdev, int i); 1156extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1145extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1157extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
@@ -1160,7 +1172,8 @@ extern int r600_irq_init(struct radeon_device *rdev);
1160extern void r600_irq_fini(struct radeon_device *rdev); 1172extern void r600_irq_fini(struct radeon_device *rdev);
1161extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1173extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1162extern int r600_irq_set(struct radeon_device *rdev); 1174extern int r600_irq_set(struct radeon_device *rdev);
1163 1175extern void r600_irq_suspend(struct radeon_device *rdev);
1176/* r600 audio */
1164extern int r600_audio_init(struct radeon_device *rdev); 1177extern int r600_audio_init(struct radeon_device *rdev);
1165extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1178extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1166extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1179extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);