diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-09-27 15:08:35 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2012-12-10 16:53:23 -0500 |
commit | 4d75658bffea78f0c6f82fd46df1ec983ccacdf0 (patch) | |
tree | a6c111fe8fb7ebb76af46924ec0bc5c8f7cc961b /drivers/gpu/drm/radeon/r600d.h | |
parent | 71bfe916ebe6d026cd3d0e41c398574fc1228e03 (diff) |
drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx
Uses the new multi-ring infrastucture. 6xx/7xx has a single
async DMA ring.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600d.h')
-rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index fa6f37099ba9..a596c554a3a0 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
@@ -590,9 +590,59 @@ | |||
590 | #define WAIT_2D_IDLECLEAN_bit (1 << 16) | 590 | #define WAIT_2D_IDLECLEAN_bit (1 << 16) |
591 | #define WAIT_3D_IDLECLEAN_bit (1 << 17) | 591 | #define WAIT_3D_IDLECLEAN_bit (1 << 17) |
592 | 592 | ||
593 | /* async DMA */ | ||
594 | #define DMA_TILING_CONFIG 0x3ec4 | ||
595 | #define DMA_CONFIG 0x3e4c | ||
596 | |||
597 | #define DMA_RB_CNTL 0xd000 | ||
598 | # define DMA_RB_ENABLE (1 << 0) | ||
599 | # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ | ||
600 | # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ | ||
601 | # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) | ||
602 | # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ | ||
603 | # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ | ||
604 | #define DMA_RB_BASE 0xd004 | ||
605 | #define DMA_RB_RPTR 0xd008 | ||
606 | #define DMA_RB_WPTR 0xd00c | ||
607 | |||
608 | #define DMA_RB_RPTR_ADDR_HI 0xd01c | ||
609 | #define DMA_RB_RPTR_ADDR_LO 0xd020 | ||
610 | |||
611 | #define DMA_IB_CNTL 0xd024 | ||
612 | # define DMA_IB_ENABLE (1 << 0) | ||
613 | # define DMA_IB_SWAP_ENABLE (1 << 4) | ||
614 | #define DMA_IB_RPTR 0xd028 | ||
615 | #define DMA_CNTL 0xd02c | ||
616 | # define TRAP_ENABLE (1 << 0) | ||
617 | # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) | ||
618 | # define SEM_WAIT_INT_ENABLE (1 << 2) | ||
619 | # define DATA_SWAP_ENABLE (1 << 3) | ||
620 | # define FENCE_SWAP_ENABLE (1 << 4) | ||
621 | # define CTXEMPTY_INT_ENABLE (1 << 28) | ||
622 | #define DMA_STATUS_REG 0xd034 | ||
623 | # define DMA_IDLE (1 << 0) | ||
624 | #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 | ||
625 | #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 | ||
626 | #define DMA_MODE 0xd0bc | ||
627 | |||
628 | /* async DMA packets */ | ||
629 | #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ | ||
630 | (((t) & 0x1) << 23) | \ | ||
631 | (((s) & 0x1) << 22) | \ | ||
632 | (((n) & 0xFFFF) << 0)) | ||
633 | /* async DMA Packet types */ | ||
634 | #define DMA_PACKET_WRITE 0x2 | ||
635 | #define DMA_PACKET_COPY 0x3 | ||
636 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 | ||
637 | #define DMA_PACKET_SEMAPHORE 0x5 | ||
638 | #define DMA_PACKET_FENCE 0x6 | ||
639 | #define DMA_PACKET_TRAP 0x7 | ||
640 | #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ | ||
641 | #define DMA_PACKET_NOP 0xf | ||
642 | |||
593 | #define IH_RB_CNTL 0x3e00 | 643 | #define IH_RB_CNTL 0x3e00 |
594 | # define IH_RB_ENABLE (1 << 0) | 644 | # define IH_RB_ENABLE (1 << 0) |
595 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ | 645 | # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ |
596 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) | 646 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
597 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) | 647 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) |
598 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ | 648 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ |
@@ -637,7 +687,9 @@ | |||
637 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 | 687 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
638 | 688 | ||
639 | #define SRBM_SOFT_RESET 0xe60 | 689 | #define SRBM_SOFT_RESET 0xe60 |
690 | # define SOFT_RESET_DMA (1 << 12) | ||
640 | # define SOFT_RESET_RLC (1 << 13) | 691 | # define SOFT_RESET_RLC (1 << 13) |
692 | # define RV770_SOFT_RESET_DMA (1 << 20) | ||
641 | 693 | ||
642 | #define CP_INT_CNTL 0xc124 | 694 | #define CP_INT_CNTL 0xc124 |
643 | # define CNTX_BUSY_INT_ENABLE (1 << 19) | 695 | # define CNTX_BUSY_INT_ENABLE (1 << 19) |