drm/radeon/kms: add a CS ioctl flag not to rewrite tiling flags in the CS

This adds a new optional chunk to the CS ioctl that specifies optional flags
to the CS parser. Why this is useful is explained below. Note that some regs
no longer need the NOP relocation packet if this feature is enabled.
Tested on r300g and r600g with this flag disabled and enabled.

Assume there are two contexts sharing the same mipmapped tiled texture.
One context wants to render into the first mipmap and the other one
wants to render into the last mipmap. As you probably know, the hardware
has a MACRO_SWITCH feature, which turns off macro tiling for small mipmaps,
but that only applies to samplers.
(at least on r300-r500, though later hardware likely behaves the same)

So we want to just re-set the tiling flags before rendering (writing
packets), right? ... No. The contexts run in parallel, so they may
set the tiling flags simultaneously and then fire their command streams
also simultaneously. The last one setting the flags wins, the other one
loses.

Another problem is when one context wants to render into the first and
the last mipmap in one CS. Impossible. It must flush before changing
tiling flags and do the rendering into the smaller mipmaps in another CS.

Yet another problem is that writing copy_blit in userspace would be a mess
involving re-setting tiling flags to please the kernel, and causing races
with other contexts at the same time.

The only way out of this is to send tiling flags with each CS, ideally
with each relocation. But we already do that through the registers.
So let's just use what we have in the registers.

Signed-off-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 16 insertions, 10 deletions

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0a2e023c1557..cb1acffd2430 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -941,7 +941,8 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                 track->db_depth_control = radeon_get_ib_value(p, idx);
                 break;
         case R_028010_DB_DEPTH_INFO:
-                if (r600_cs_packet_next_is_pkt3_nop(p)) {
+                if (!p->keep_tiling_flags &&
+                    r600_cs_packet_next_is_pkt3_nop(p)) {
                         r = r600_cs_packet_next_reloc(p, &reloc);
                         if (r) {
                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
@@ -992,7 +993,8 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case R_0280B4_CB_COLOR5_INFO:
         case R_0280B8_CB_COLOR6_INFO:
         case R_0280BC_CB_COLOR7_INFO:
-                if (r600_cs_packet_next_is_pkt3_nop(p)) {
+                if (!p->keep_tiling_flags &&
+                     r600_cs_packet_next_is_pkt3_nop(p)) {
                         r = r600_cs_packet_next_reloc(p, &reloc);
                         if (r) {
                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
@@ -1291,10 +1293,12 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
         mip_offset <<= 8;
 
         word0 = radeon_get_ib_value(p, idx + 0);
-        if (tiling_flags & RADEON_TILING_MACRO)
-                word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
-        else if (tiling_flags & RADEON_TILING_MICRO)
-                word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+        if (!p->keep_tiling_flags) {
+                if (tiling_flags & RADEON_TILING_MACRO)
+                        word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+                else if (tiling_flags & RADEON_TILING_MICRO)
+                        word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+        }
         word1 = radeon_get_ib_value(p, idx + 1);
         w0 = G_038000_TEX_WIDTH(word0) + 1;
         h0 = G_038004_TEX_HEIGHT(word1) + 1;
@@ -1621,10 +1625,12 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                         return -EINVAL;
                                 }
                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
-                                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                                        ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
-                                else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-                                        ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+                                if (!p->keep_tiling_flags) {
+                                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                                ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+                                        else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                                ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+                                }
                                 texture = reloc->robj;
                                 /* tex mip base */
                                 r = r600_cs_packet_next_reloc(p, &reloc);