diff options
author | Andi Kleen <ak@linux.intel.com> | 2011-10-13 19:08:41 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-10-18 04:44:20 -0400 |
commit | 488479ebcbdfabbc4d2ae3fab13971bba3ced605 (patch) | |
tree | 68f3921349cd17d510b8f8566cb1fb92a9e0c28b /drivers/gpu/drm/radeon/r600_cs.c | |
parent | 1c482ab3596b8ee4c635926b35ee88ad56ba2f9c (diff) |
drm/radeon: Drop inlines from evergreen_cs.c / r600_cs.c
Fixes
evergreen_cs_parse 4080 23124 +19044
and others compared to a non force inline kernel.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_cs.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index cf83aa05a684..7339c0bd9562 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -162,7 +162,7 @@ static const struct gpu_formats color_formats_table[] = { | |||
162 | [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, | 162 | [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, |
163 | }; | 163 | }; |
164 | 164 | ||
165 | static inline bool fmt_is_valid_color(u32 format) | 165 | static bool fmt_is_valid_color(u32 format) |
166 | { | 166 | { |
167 | if (format >= ARRAY_SIZE(color_formats_table)) | 167 | if (format >= ARRAY_SIZE(color_formats_table)) |
168 | return false; | 168 | return false; |
@@ -173,7 +173,7 @@ static inline bool fmt_is_valid_color(u32 format) | |||
173 | return false; | 173 | return false; |
174 | } | 174 | } |
175 | 175 | ||
176 | static inline bool fmt_is_valid_texture(u32 format, enum radeon_family family) | 176 | static bool fmt_is_valid_texture(u32 format, enum radeon_family family) |
177 | { | 177 | { |
178 | if (format >= ARRAY_SIZE(color_formats_table)) | 178 | if (format >= ARRAY_SIZE(color_formats_table)) |
179 | return false; | 179 | return false; |
@@ -187,7 +187,7 @@ static inline bool fmt_is_valid_texture(u32 format, enum radeon_family family) | |||
187 | return false; | 187 | return false; |
188 | } | 188 | } |
189 | 189 | ||
190 | static inline int fmt_get_blocksize(u32 format) | 190 | static int fmt_get_blocksize(u32 format) |
191 | { | 191 | { |
192 | if (format >= ARRAY_SIZE(color_formats_table)) | 192 | if (format >= ARRAY_SIZE(color_formats_table)) |
193 | return 0; | 193 | return 0; |
@@ -195,7 +195,7 @@ static inline int fmt_get_blocksize(u32 format) | |||
195 | return color_formats_table[format].blocksize; | 195 | return color_formats_table[format].blocksize; |
196 | } | 196 | } |
197 | 197 | ||
198 | static inline int fmt_get_nblocksx(u32 format, u32 w) | 198 | static int fmt_get_nblocksx(u32 format, u32 w) |
199 | { | 199 | { |
200 | unsigned bw; | 200 | unsigned bw; |
201 | 201 | ||
@@ -209,7 +209,7 @@ static inline int fmt_get_nblocksx(u32 format, u32 w) | |||
209 | return (w + bw - 1) / bw; | 209 | return (w + bw - 1) / bw; |
210 | } | 210 | } |
211 | 211 | ||
212 | static inline int fmt_get_nblocksy(u32 format, u32 h) | 212 | static int fmt_get_nblocksy(u32 format, u32 h) |
213 | { | 213 | { |
214 | unsigned bh; | 214 | unsigned bh; |
215 | 215 | ||
@@ -223,7 +223,7 @@ static inline int fmt_get_nblocksy(u32 format, u32 h) | |||
223 | return (h + bh - 1) / bh; | 223 | return (h + bh - 1) / bh; |
224 | } | 224 | } |
225 | 225 | ||
226 | static inline int r600_bpe_from_format(u32 *bpe, u32 format) | 226 | static int r600_bpe_from_format(u32 *bpe, u32 format) |
227 | { | 227 | { |
228 | unsigned res; | 228 | unsigned res; |
229 | 229 | ||
@@ -252,7 +252,7 @@ struct array_mode_checker { | |||
252 | }; | 252 | }; |
253 | 253 | ||
254 | /* returns alignment in pixels for pitch/height/depth and bytes for base */ | 254 | /* returns alignment in pixels for pitch/height/depth and bytes for base */ |
255 | static inline int r600_get_array_mode_alignment(struct array_mode_checker *values, | 255 | static int r600_get_array_mode_alignment(struct array_mode_checker *values, |
256 | u32 *pitch_align, | 256 | u32 *pitch_align, |
257 | u32 *height_align, | 257 | u32 *height_align, |
258 | u32 *depth_align, | 258 | u32 *depth_align, |
@@ -331,7 +331,7 @@ static void r600_cs_track_init(struct r600_cs_track *track) | |||
331 | track->db_depth_control = 0xFFFFFFFF; | 331 | track->db_depth_control = 0xFFFFFFFF; |
332 | } | 332 | } |
333 | 333 | ||
334 | static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | 334 | static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) |
335 | { | 335 | { |
336 | struct r600_cs_track *track = p->track; | 336 | struct r600_cs_track *track = p->track; |
337 | u32 slice_tile_max, size, tmp; | 337 | u32 slice_tile_max, size, tmp; |
@@ -737,7 +737,7 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, | |||
737 | * Check next packet is relocation packet3, do bo validation and compute | 737 | * Check next packet is relocation packet3, do bo validation and compute |
738 | * GPU offset using the provided start. | 738 | * GPU offset using the provided start. |
739 | **/ | 739 | **/ |
740 | static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) | 740 | static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) |
741 | { | 741 | { |
742 | struct radeon_cs_packet p3reloc; | 742 | struct radeon_cs_packet p3reloc; |
743 | int r; | 743 | int r; |
@@ -911,7 +911,7 @@ static int r600_cs_parse_packet0(struct radeon_cs_parser *p, | |||
911 | * if register is safe. If register is not flag as safe this function | 911 | * if register is safe. If register is not flag as safe this function |
912 | * will test it against a list of register needind special handling. | 912 | * will test it against a list of register needind special handling. |
913 | */ | 913 | */ |
914 | static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) | 914 | static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) |
915 | { | 915 | { |
916 | struct r600_cs_track *track = (struct r600_cs_track *)p->track; | 916 | struct r600_cs_track *track = (struct r600_cs_track *)p->track; |
917 | struct radeon_cs_reloc *reloc; | 917 | struct radeon_cs_reloc *reloc; |
@@ -1215,7 +1215,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx | |||
1215 | return 0; | 1215 | return 0; |
1216 | } | 1216 | } |
1217 | 1217 | ||
1218 | static inline unsigned mip_minify(unsigned size, unsigned level) | 1218 | static unsigned mip_minify(unsigned size, unsigned level) |
1219 | { | 1219 | { |
1220 | unsigned val; | 1220 | unsigned val; |
1221 | 1221 | ||
@@ -1285,7 +1285,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, | |||
1285 | * This function will check that the resource has valid field and that | 1285 | * This function will check that the resource has valid field and that |
1286 | * the texture and mipmap bo object are big enough to cover this resource. | 1286 | * the texture and mipmap bo object are big enough to cover this resource. |
1287 | */ | 1287 | */ |
1288 | static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, | 1288 | static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, |
1289 | struct radeon_bo *texture, | 1289 | struct radeon_bo *texture, |
1290 | struct radeon_bo *mipmap, | 1290 | struct radeon_bo *mipmap, |
1291 | u64 base_offset, | 1291 | u64 base_offset, |