diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2010-11-14 20:24:35 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-11-17 23:55:37 -0500 |
commit | 16790569eddf4d406a16a65f4750f405fa669c52 (patch) | |
tree | d43fd3e94ecb0a7548863ffbe9b7aa4ad5cdfaff /drivers/gpu/drm/radeon/r600_cs.c | |
parent | 0143832cc96d0bf78486297aad5c8fb2c2ead02a (diff) |
drm/radeon/kms: fix and unify tiled buffer alignment checking for r6xx/7xx
Tiled buffers have the same alignment requirements regardless of
whether the surface is for db, cb, or textures. Previously, the
calculations where inconsistent for each buffer type.
- Unify the alignment calculations in a common function
- Standardize the alignment units (pixels for pitch/height/depth,
bytes for base)
- properly check the buffer base alignments
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_cs.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 309 |
1 files changed, 193 insertions, 116 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 37cc2aa9f923..0f90fc3482ce 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -50,6 +50,7 @@ struct r600_cs_track { | |||
50 | u32 nsamples; | 50 | u32 nsamples; |
51 | u32 cb_color_base_last[8]; | 51 | u32 cb_color_base_last[8]; |
52 | struct radeon_bo *cb_color_bo[8]; | 52 | struct radeon_bo *cb_color_bo[8]; |
53 | u64 cb_color_bo_mc[8]; | ||
53 | u32 cb_color_bo_offset[8]; | 54 | u32 cb_color_bo_offset[8]; |
54 | struct radeon_bo *cb_color_frag_bo[8]; | 55 | struct radeon_bo *cb_color_frag_bo[8]; |
55 | struct radeon_bo *cb_color_tile_bo[8]; | 56 | struct radeon_bo *cb_color_tile_bo[8]; |
@@ -67,6 +68,7 @@ struct r600_cs_track { | |||
67 | u32 db_depth_size; | 68 | u32 db_depth_size; |
68 | u32 db_offset; | 69 | u32 db_offset; |
69 | struct radeon_bo *db_bo; | 70 | struct radeon_bo *db_bo; |
71 | u64 db_bo_mc; | ||
70 | }; | 72 | }; |
71 | 73 | ||
72 | static inline int r600_bpe_from_format(u32 *bpe, u32 format) | 74 | static inline int r600_bpe_from_format(u32 *bpe, u32 format) |
@@ -140,6 +142,68 @@ static inline int r600_bpe_from_format(u32 *bpe, u32 format) | |||
140 | return 0; | 142 | return 0; |
141 | } | 143 | } |
142 | 144 | ||
145 | struct array_mode_checker { | ||
146 | int array_mode; | ||
147 | u32 group_size; | ||
148 | u32 nbanks; | ||
149 | u32 npipes; | ||
150 | u32 nsamples; | ||
151 | u32 bpe; | ||
152 | }; | ||
153 | |||
154 | /* returns alignment in pixels for pitch/height/depth and bytes for base */ | ||
155 | static inline int r600_get_array_mode_alignment(struct array_mode_checker *values, | ||
156 | u32 *pitch_align, | ||
157 | u32 *height_align, | ||
158 | u32 *depth_align, | ||
159 | u64 *base_align) | ||
160 | { | ||
161 | u32 tile_width = 8; | ||
162 | u32 tile_height = 8; | ||
163 | u32 macro_tile_width = values->nbanks; | ||
164 | u32 macro_tile_height = values->npipes; | ||
165 | u32 tile_bytes = tile_width * tile_height * values->bpe * values->nsamples; | ||
166 | u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes; | ||
167 | |||
168 | switch (values->array_mode) { | ||
169 | case ARRAY_LINEAR_GENERAL: | ||
170 | /* technically tile_width/_height for pitch/height */ | ||
171 | *pitch_align = 1; /* tile_width */ | ||
172 | *height_align = 1; /* tile_height */ | ||
173 | *depth_align = 1; | ||
174 | *base_align = 1; | ||
175 | break; | ||
176 | case ARRAY_LINEAR_ALIGNED: | ||
177 | *pitch_align = max((u32)64, (u32)(values->group_size / values->bpe)); | ||
178 | *height_align = tile_height; | ||
179 | *depth_align = 1; | ||
180 | *base_align = values->group_size; | ||
181 | break; | ||
182 | case ARRAY_1D_TILED_THIN1: | ||
183 | *pitch_align = max((u32)tile_width, | ||
184 | (u32)(values->group_size / | ||
185 | (tile_height * values->bpe * values->nsamples))); | ||
186 | *height_align = tile_height; | ||
187 | *depth_align = 1; | ||
188 | *base_align = values->group_size; | ||
189 | break; | ||
190 | case ARRAY_2D_TILED_THIN1: | ||
191 | *pitch_align = max((u32)macro_tile_width, | ||
192 | (u32)(((values->group_size / tile_height) / | ||
193 | (values->bpe * values->nsamples)) * | ||
194 | values->nbanks)) * tile_width; | ||
195 | *height_align = macro_tile_height * tile_height; | ||
196 | *depth_align = 1; | ||
197 | *base_align = max(macro_tile_bytes, | ||
198 | (*pitch_align) * values->bpe * (*height_align) * values->nsamples); | ||
199 | break; | ||
200 | default: | ||
201 | return -EINVAL; | ||
202 | } | ||
203 | |||
204 | return 0; | ||
205 | } | ||
206 | |||
143 | static void r600_cs_track_init(struct r600_cs_track *track) | 207 | static void r600_cs_track_init(struct r600_cs_track *track) |
144 | { | 208 | { |
145 | int i; | 209 | int i; |
@@ -153,10 +217,12 @@ static void r600_cs_track_init(struct r600_cs_track *track) | |||
153 | track->cb_color_info[i] = 0; | 217 | track->cb_color_info[i] = 0; |
154 | track->cb_color_bo[i] = NULL; | 218 | track->cb_color_bo[i] = NULL; |
155 | track->cb_color_bo_offset[i] = 0xFFFFFFFF; | 219 | track->cb_color_bo_offset[i] = 0xFFFFFFFF; |
220 | track->cb_color_bo_mc[i] = 0xFFFFFFFF; | ||
156 | } | 221 | } |
157 | track->cb_target_mask = 0xFFFFFFFF; | 222 | track->cb_target_mask = 0xFFFFFFFF; |
158 | track->cb_shader_mask = 0xFFFFFFFF; | 223 | track->cb_shader_mask = 0xFFFFFFFF; |
159 | track->db_bo = NULL; | 224 | track->db_bo = NULL; |
225 | track->db_bo_mc = 0xFFFFFFFF; | ||
160 | /* assume the biggest format and that htile is enabled */ | 226 | /* assume the biggest format and that htile is enabled */ |
161 | track->db_depth_info = 7 | (1 << 25); | 227 | track->db_depth_info = 7 | (1 << 25); |
162 | track->db_depth_view = 0xFFFFC000; | 228 | track->db_depth_view = 0xFFFFC000; |
@@ -168,7 +234,10 @@ static void r600_cs_track_init(struct r600_cs_track *track) | |||
168 | static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | 234 | static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) |
169 | { | 235 | { |
170 | struct r600_cs_track *track = p->track; | 236 | struct r600_cs_track *track = p->track; |
171 | u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align; | 237 | u32 bpe = 0, slice_tile_max, size, tmp; |
238 | u32 height, height_align, pitch, pitch_align, depth_align; | ||
239 | u64 base_offset, base_align; | ||
240 | struct array_mode_checker array_check; | ||
172 | volatile u32 *ib = p->ib->ptr; | 241 | volatile u32 *ib = p->ib->ptr; |
173 | unsigned array_mode; | 242 | unsigned array_mode; |
174 | 243 | ||
@@ -183,60 +252,40 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
183 | i, track->cb_color_info[i]); | 252 | i, track->cb_color_info[i]); |
184 | return -EINVAL; | 253 | return -EINVAL; |
185 | } | 254 | } |
186 | /* pitch is the number of 8x8 tiles per row */ | 255 | /* pitch in pixels */ |
187 | pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1; | 256 | pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; |
188 | slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; | 257 | slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; |
189 | slice_tile_max *= 64; | 258 | slice_tile_max *= 64; |
190 | height = slice_tile_max / (pitch * 8); | 259 | height = slice_tile_max / pitch; |
191 | if (height > 8192) | 260 | if (height > 8192) |
192 | height = 8192; | 261 | height = 8192; |
193 | array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); | 262 | array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); |
263 | |||
264 | base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; | ||
265 | array_check.array_mode = array_mode; | ||
266 | array_check.group_size = track->group_size; | ||
267 | array_check.nbanks = track->nbanks; | ||
268 | array_check.npipes = track->npipes; | ||
269 | array_check.nsamples = track->nsamples; | ||
270 | array_check.bpe = bpe; | ||
271 | if (r600_get_array_mode_alignment(&array_check, | ||
272 | &pitch_align, &height_align, &depth_align, &base_align)) { | ||
273 | dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, | ||
274 | G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, | ||
275 | track->cb_color_info[i]); | ||
276 | return -EINVAL; | ||
277 | } | ||
194 | switch (array_mode) { | 278 | switch (array_mode) { |
195 | case V_0280A0_ARRAY_LINEAR_GENERAL: | 279 | case V_0280A0_ARRAY_LINEAR_GENERAL: |
196 | /* technically height & 0x7 */ | ||
197 | break; | 280 | break; |
198 | case V_0280A0_ARRAY_LINEAR_ALIGNED: | 281 | case V_0280A0_ARRAY_LINEAR_ALIGNED: |
199 | pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8; | ||
200 | if (!IS_ALIGNED(pitch, pitch_align)) { | ||
201 | dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", | ||
202 | __func__, __LINE__, pitch); | ||
203 | return -EINVAL; | ||
204 | } | ||
205 | if (!IS_ALIGNED(height, 8)) { | ||
206 | dev_warn(p->dev, "%s:%d cb height (%d) invalid\n", | ||
207 | __func__, __LINE__, height); | ||
208 | return -EINVAL; | ||
209 | } | ||
210 | break; | 282 | break; |
211 | case V_0280A0_ARRAY_1D_TILED_THIN1: | 283 | case V_0280A0_ARRAY_1D_TILED_THIN1: |
212 | pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8; | ||
213 | if (!IS_ALIGNED(pitch, pitch_align)) { | ||
214 | dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", | ||
215 | __func__, __LINE__, pitch); | ||
216 | return -EINVAL; | ||
217 | } | ||
218 | /* avoid breaking userspace */ | 284 | /* avoid breaking userspace */ |
219 | if (height > 7) | 285 | if (height > 7) |
220 | height &= ~0x7; | 286 | height &= ~0x7; |
221 | if (!IS_ALIGNED(height, 8)) { | ||
222 | dev_warn(p->dev, "%s:%d cb height (%d) invalid\n", | ||
223 | __func__, __LINE__, height); | ||
224 | return -EINVAL; | ||
225 | } | ||
226 | break; | 287 | break; |
227 | case V_0280A0_ARRAY_2D_TILED_THIN1: | 288 | case V_0280A0_ARRAY_2D_TILED_THIN1: |
228 | pitch_align = max((u32)track->nbanks, | ||
229 | (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks)) / 8; | ||
230 | if (!IS_ALIGNED(pitch, pitch_align)) { | ||
231 | dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", | ||
232 | __func__, __LINE__, pitch); | ||
233 | return -EINVAL; | ||
234 | } | ||
235 | if (!IS_ALIGNED((height / 8), track->npipes)) { | ||
236 | dev_warn(p->dev, "%s:%d cb height (%d) invalid\n", | ||
237 | __func__, __LINE__, height); | ||
238 | return -EINVAL; | ||
239 | } | ||
240 | break; | 289 | break; |
241 | default: | 290 | default: |
242 | dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, | 291 | dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, |
@@ -244,8 +293,24 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
244 | track->cb_color_info[i]); | 293 | track->cb_color_info[i]); |
245 | return -EINVAL; | 294 | return -EINVAL; |
246 | } | 295 | } |
296 | |||
297 | if (!IS_ALIGNED(pitch, pitch_align)) { | ||
298 | dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", | ||
299 | __func__, __LINE__, pitch); | ||
300 | return -EINVAL; | ||
301 | } | ||
302 | if (!IS_ALIGNED(height, height_align)) { | ||
303 | dev_warn(p->dev, "%s:%d cb height (%d) invalid\n", | ||
304 | __func__, __LINE__, height); | ||
305 | return -EINVAL; | ||
306 | } | ||
307 | if (!IS_ALIGNED(base_offset, base_align)) { | ||
308 | dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); | ||
309 | return -EINVAL; | ||
310 | } | ||
311 | |||
247 | /* check offset */ | 312 | /* check offset */ |
248 | tmp = height * pitch * 8 * bpe; | 313 | tmp = height * pitch * bpe; |
249 | if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { | 314 | if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { |
250 | if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { | 315 | if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { |
251 | /* the initial DDX does bad things with the CB size occasionally */ | 316 | /* the initial DDX does bad things with the CB size occasionally */ |
@@ -260,15 +325,11 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
260 | return -EINVAL; | 325 | return -EINVAL; |
261 | } | 326 | } |
262 | } | 327 | } |
263 | if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) { | ||
264 | dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]); | ||
265 | return -EINVAL; | ||
266 | } | ||
267 | /* limit max tile */ | 328 | /* limit max tile */ |
268 | tmp = (height * pitch * 8) >> 6; | 329 | tmp = (height * pitch) >> 6; |
269 | if (tmp < slice_tile_max) | 330 | if (tmp < slice_tile_max) |
270 | slice_tile_max = tmp; | 331 | slice_tile_max = tmp; |
271 | tmp = S_028060_PITCH_TILE_MAX(pitch - 1) | | 332 | tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | |
272 | S_028060_SLICE_TILE_MAX(slice_tile_max - 1); | 333 | S_028060_SLICE_TILE_MAX(slice_tile_max - 1); |
273 | ib[track->cb_color_size_idx[i]] = tmp; | 334 | ib[track->cb_color_size_idx[i]] = tmp; |
274 | return 0; | 335 | return 0; |
@@ -310,7 +371,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
310 | /* Check depth buffer */ | 371 | /* Check depth buffer */ |
311 | if (G_028800_STENCIL_ENABLE(track->db_depth_control) || | 372 | if (G_028800_STENCIL_ENABLE(track->db_depth_control) || |
312 | G_028800_Z_ENABLE(track->db_depth_control)) { | 373 | G_028800_Z_ENABLE(track->db_depth_control)) { |
313 | u32 nviews, bpe, ntiles, pitch, pitch_align, height, size, slice_tile_max; | 374 | u32 nviews, bpe, ntiles, size, slice_tile_max; |
375 | u32 height, height_align, pitch, pitch_align, depth_align; | ||
376 | u64 base_offset, base_align; | ||
377 | struct array_mode_checker array_check; | ||
378 | int array_mode; | ||
379 | |||
314 | if (track->db_bo == NULL) { | 380 | if (track->db_bo == NULL) { |
315 | dev_warn(p->dev, "z/stencil with no depth buffer\n"); | 381 | dev_warn(p->dev, "z/stencil with no depth buffer\n"); |
316 | return -EINVAL; | 382 | return -EINVAL; |
@@ -353,41 +419,34 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
353 | ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); | 419 | ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); |
354 | } else { | 420 | } else { |
355 | size = radeon_bo_size(track->db_bo); | 421 | size = radeon_bo_size(track->db_bo); |
356 | pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1; | 422 | /* pitch in pixels */ |
423 | pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; | ||
357 | slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; | 424 | slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; |
358 | slice_tile_max *= 64; | 425 | slice_tile_max *= 64; |
359 | height = slice_tile_max / (pitch * 8); | 426 | height = slice_tile_max / pitch; |
360 | if (height > 8192) | 427 | if (height > 8192) |
361 | height = 8192; | 428 | height = 8192; |
362 | switch (G_028010_ARRAY_MODE(track->db_depth_info)) { | 429 | base_offset = track->db_bo_mc + track->db_offset; |
430 | array_mode = G_028010_ARRAY_MODE(track->db_depth_info); | ||
431 | array_check.array_mode = array_mode; | ||
432 | array_check.group_size = track->group_size; | ||
433 | array_check.nbanks = track->nbanks; | ||
434 | array_check.npipes = track->npipes; | ||
435 | array_check.nsamples = track->nsamples; | ||
436 | array_check.bpe = bpe; | ||
437 | if (r600_get_array_mode_alignment(&array_check, | ||
438 | &pitch_align, &height_align, &depth_align, &base_align)) { | ||
439 | dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, | ||
440 | G_028010_ARRAY_MODE(track->db_depth_info), | ||
441 | track->db_depth_info); | ||
442 | return -EINVAL; | ||
443 | } | ||
444 | switch (array_mode) { | ||
363 | case V_028010_ARRAY_1D_TILED_THIN1: | 445 | case V_028010_ARRAY_1D_TILED_THIN1: |
364 | pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8); | ||
365 | if (!IS_ALIGNED(pitch, pitch_align)) { | ||
366 | dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n", | ||
367 | __func__, __LINE__, pitch); | ||
368 | return -EINVAL; | ||
369 | } | ||
370 | /* don't break userspace */ | 446 | /* don't break userspace */ |
371 | height &= ~0x7; | 447 | height &= ~0x7; |
372 | if (!IS_ALIGNED(height, 8)) { | ||
373 | dev_warn(p->dev, "%s:%d db height (%d) invalid\n", | ||
374 | __func__, __LINE__, height); | ||
375 | return -EINVAL; | ||
376 | } | ||
377 | break; | 448 | break; |
378 | case V_028010_ARRAY_2D_TILED_THIN1: | 449 | case V_028010_ARRAY_2D_TILED_THIN1: |
379 | pitch_align = max((u32)track->nbanks, | ||
380 | (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8; | ||
381 | if (!IS_ALIGNED(pitch, pitch_align)) { | ||
382 | dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n", | ||
383 | __func__, __LINE__, pitch); | ||
384 | return -EINVAL; | ||
385 | } | ||
386 | if (!IS_ALIGNED((height / 8), track->npipes)) { | ||
387 | dev_warn(p->dev, "%s:%d db height (%d) invalid\n", | ||
388 | __func__, __LINE__, height); | ||
389 | return -EINVAL; | ||
390 | } | ||
391 | break; | 450 | break; |
392 | default: | 451 | default: |
393 | dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, | 452 | dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, |
@@ -395,15 +454,27 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
395 | track->db_depth_info); | 454 | track->db_depth_info); |
396 | return -EINVAL; | 455 | return -EINVAL; |
397 | } | 456 | } |
398 | if (!IS_ALIGNED(track->db_offset, track->group_size)) { | 457 | |
399 | dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset); | 458 | if (!IS_ALIGNED(pitch, pitch_align)) { |
459 | dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n", | ||
460 | __func__, __LINE__, pitch); | ||
461 | return -EINVAL; | ||
462 | } | ||
463 | if (!IS_ALIGNED(height, height_align)) { | ||
464 | dev_warn(p->dev, "%s:%d db height (%d) invalid\n", | ||
465 | __func__, __LINE__, height); | ||
400 | return -EINVAL; | 466 | return -EINVAL; |
401 | } | 467 | } |
468 | if (!IS_ALIGNED(base_offset, base_align)) { | ||
469 | dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); | ||
470 | return -EINVAL; | ||
471 | } | ||
472 | |||
402 | ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; | 473 | ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; |
403 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; | 474 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; |
404 | tmp = ntiles * bpe * 64 * nviews; | 475 | tmp = ntiles * bpe * 64 * nviews; |
405 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { | 476 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { |
406 | dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n", | 477 | dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %u have %lu)\n", |
407 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, | 478 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, |
408 | radeon_bo_size(track->db_bo)); | 479 | radeon_bo_size(track->db_bo)); |
409 | return -EINVAL; | 480 | return -EINVAL; |
@@ -954,6 +1025,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx | |||
954 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1025 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
955 | track->cb_color_base_last[tmp] = ib[idx]; | 1026 | track->cb_color_base_last[tmp] = ib[idx]; |
956 | track->cb_color_bo[tmp] = reloc->robj; | 1027 | track->cb_color_bo[tmp] = reloc->robj; |
1028 | track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; | ||
957 | break; | 1029 | break; |
958 | case DB_DEPTH_BASE: | 1030 | case DB_DEPTH_BASE: |
959 | r = r600_cs_packet_next_reloc(p, &reloc); | 1031 | r = r600_cs_packet_next_reloc(p, &reloc); |
@@ -965,6 +1037,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx | |||
965 | track->db_offset = radeon_get_ib_value(p, idx) << 8; | 1037 | track->db_offset = radeon_get_ib_value(p, idx) << 8; |
966 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1038 | ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
967 | track->db_bo = reloc->robj; | 1039 | track->db_bo = reloc->robj; |
1040 | track->db_bo_mc = reloc->lobj.gpu_offset; | ||
968 | break; | 1041 | break; |
969 | case DB_HTILE_DATA_BASE: | 1042 | case DB_HTILE_DATA_BASE: |
970 | case SQ_PGM_START_FS: | 1043 | case SQ_PGM_START_FS: |
@@ -1086,16 +1159,25 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels | |||
1086 | static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, | 1159 | static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, |
1087 | struct radeon_bo *texture, | 1160 | struct radeon_bo *texture, |
1088 | struct radeon_bo *mipmap, | 1161 | struct radeon_bo *mipmap, |
1162 | u64 base_offset, | ||
1163 | u64 mip_offset, | ||
1089 | u32 tiling_flags) | 1164 | u32 tiling_flags) |
1090 | { | 1165 | { |
1091 | struct r600_cs_track *track = p->track; | 1166 | struct r600_cs_track *track = p->track; |
1092 | u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0; | 1167 | u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0; |
1093 | u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align; | 1168 | u32 word0, word1, l0_size, mipmap_size; |
1169 | u32 height_align, pitch, pitch_align, depth_align; | ||
1170 | u64 base_align; | ||
1171 | struct array_mode_checker array_check; | ||
1094 | 1172 | ||
1095 | /* on legacy kernel we don't perform advanced check */ | 1173 | /* on legacy kernel we don't perform advanced check */ |
1096 | if (p->rdev == NULL) | 1174 | if (p->rdev == NULL) |
1097 | return 0; | 1175 | return 0; |
1098 | 1176 | ||
1177 | /* convert to bytes */ | ||
1178 | base_offset <<= 8; | ||
1179 | mip_offset <<= 8; | ||
1180 | |||
1099 | word0 = radeon_get_ib_value(p, idx + 0); | 1181 | word0 = radeon_get_ib_value(p, idx + 0); |
1100 | if (tiling_flags & RADEON_TILING_MACRO) | 1182 | if (tiling_flags & RADEON_TILING_MACRO) |
1101 | word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); | 1183 | word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); |
@@ -1128,46 +1210,38 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i | |||
1128 | return -EINVAL; | 1210 | return -EINVAL; |
1129 | } | 1211 | } |
1130 | 1212 | ||
1131 | pitch = G_038000_PITCH(word0) + 1; | 1213 | /* pitch in texels */ |
1132 | switch (G_038000_TILE_MODE(word0)) { | 1214 | pitch = (G_038000_PITCH(word0) + 1) * 8; |
1133 | case V_038000_ARRAY_LINEAR_GENERAL: | 1215 | array_check.array_mode = G_038000_TILE_MODE(word0); |
1134 | pitch_align = 1; | 1216 | array_check.group_size = track->group_size; |
1135 | /* XXX check height align */ | 1217 | array_check.nbanks = track->nbanks; |
1136 | break; | 1218 | array_check.npipes = track->npipes; |
1137 | case V_038000_ARRAY_LINEAR_ALIGNED: | 1219 | array_check.nsamples = 1; |
1138 | pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8; | 1220 | array_check.bpe = bpe; |
1139 | if (!IS_ALIGNED(pitch, pitch_align)) { | 1221 | if (r600_get_array_mode_alignment(&array_check, |
1140 | dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", | 1222 | &pitch_align, &height_align, &depth_align, &base_align)) { |
1141 | __func__, __LINE__, pitch); | 1223 | dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", |
1142 | return -EINVAL; | 1224 | __func__, __LINE__, G_038000_TILE_MODE(word0)); |
1143 | } | 1225 | return -EINVAL; |
1144 | /* XXX check height align */ | 1226 | } |
1145 | break; | 1227 | |
1146 | case V_038000_ARRAY_1D_TILED_THIN1: | 1228 | /* XXX check height as well... */ |
1147 | pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8; | 1229 | |
1148 | if (!IS_ALIGNED(pitch, pitch_align)) { | 1230 | if (!IS_ALIGNED(pitch, pitch_align)) { |
1149 | dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", | 1231 | dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", |
1150 | __func__, __LINE__, pitch); | 1232 | __func__, __LINE__, pitch); |
1151 | return -EINVAL; | 1233 | return -EINVAL; |
1152 | } | 1234 | } |
1153 | /* XXX check height align */ | 1235 | if (!IS_ALIGNED(base_offset, base_align)) { |
1154 | break; | 1236 | dev_warn(p->dev, "%s:%d tex base offset (0x%llx) invalid\n", |
1155 | case V_038000_ARRAY_2D_TILED_THIN1: | 1237 | __func__, __LINE__, base_offset); |
1156 | pitch_align = max((u32)track->nbanks, | 1238 | return -EINVAL; |
1157 | (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8; | 1239 | } |
1158 | if (!IS_ALIGNED(pitch, pitch_align)) { | 1240 | if (!IS_ALIGNED(mip_offset, base_align)) { |
1159 | dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", | 1241 | dev_warn(p->dev, "%s:%d tex mip offset (0x%llx) invalid\n", |
1160 | __func__, __LINE__, pitch); | 1242 | __func__, __LINE__, mip_offset); |
1161 | return -EINVAL; | ||
1162 | } | ||
1163 | /* XXX check height align */ | ||
1164 | break; | ||
1165 | default: | ||
1166 | dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, | ||
1167 | G_038000_TILE_MODE(word0), word0); | ||
1168 | return -EINVAL; | 1243 | return -EINVAL; |
1169 | } | 1244 | } |
1170 | /* XXX check offset align */ | ||
1171 | 1245 | ||
1172 | word0 = radeon_get_ib_value(p, idx + 4); | 1246 | word0 = radeon_get_ib_value(p, idx + 4); |
1173 | word1 = radeon_get_ib_value(p, idx + 5); | 1247 | word1 = radeon_get_ib_value(p, idx + 5); |
@@ -1402,7 +1476,10 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
1402 | mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); | 1476 | mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); |
1403 | mipmap = reloc->robj; | 1477 | mipmap = reloc->robj; |
1404 | r = r600_check_texture_resource(p, idx+(i*7)+1, | 1478 | r = r600_check_texture_resource(p, idx+(i*7)+1, |
1405 | texture, mipmap, reloc->lobj.tiling_flags); | 1479 | texture, mipmap, |
1480 | base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), | ||
1481 | mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), | ||
1482 | reloc->lobj.tiling_flags); | ||
1406 | if (r) | 1483 | if (r) |
1407 | return r; | 1484 | return r; |
1408 | ib[idx+1+(i*7)+2] += base_offset; | 1485 | ib[idx+1+(i*7)+2] += base_offset; |