drm/radeon/kms/r600: reduce gpu cache flushing

Only flush the gpu caches before we submit a fence.
This leads to a small performance boost when we take
the extra gpu cache flushes out of the ddx and mesa.
Once this patch is in and the drm version is bumped,
we can remove the flushes from the ddx and drm.

Also, remove the extra cache flushes from the blit
routine.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 9661a469f3bd..7c32a233b236 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1783,6 +1783,13 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
                           struct radeon_fence *fence)
 {
         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
+
+        radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
+        radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
+        /* wait for 3D idle clean */
+        radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+        radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+        radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
         /* Emit fence sequence & fire IRQ */
         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));