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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/gpu/drm/radeon/r520.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/gpu/drm/radeon/r520.c')
-rw-r--r--drivers/gpu/drm/radeon/r520.c42
1 files changed, 23 insertions, 19 deletions
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index f7435185c0a6..3c44b8d39318 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -27,6 +27,7 @@
27 */ 27 */
28#include "drmP.h" 28#include "drmP.h"
29#include "radeon.h" 29#include "radeon.h"
30#include "radeon_asic.h"
30#include "atom.h" 31#include "atom.h"
31#include "r520d.h" 32#include "r520d.h"
32 33
@@ -119,19 +120,15 @@ static void r520_vram_get_type(struct radeon_device *rdev)
119 rdev->mc.vram_width *= 2; 120 rdev->mc.vram_width *= 2;
120} 121}
121 122
122void r520_vram_info(struct radeon_device *rdev) 123void r520_mc_init(struct radeon_device *rdev)
123{ 124{
124 fixed20_12 a;
125 125
126 r520_vram_get_type(rdev); 126 r520_vram_get_type(rdev);
127
128 r100_vram_init_sizes(rdev); 127 r100_vram_init_sizes(rdev);
129 /* FIXME: we should enforce default clock in case GPU is not in 128 radeon_vram_location(rdev, &rdev->mc, 0);
130 * default setup 129 if (!(rdev->flags & RADEON_IS_AGP))
131 */ 130 radeon_gtt_location(rdev, &rdev->mc);
132 a.full = rfixed_const(100); 131 radeon_update_bandwidth_info(rdev);
133 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
134 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
135} 132}
136 133
137void r520_mc_program(struct radeon_device *rdev) 134void r520_mc_program(struct radeon_device *rdev)
@@ -185,8 +182,8 @@ static int r520_startup(struct radeon_device *rdev)
185 return r; 182 return r;
186 } 183 }
187 /* Enable IRQ */ 184 /* Enable IRQ */
188 rdev->irq.sw_int = true;
189 rs600_irq_set(rdev); 185 rs600_irq_set(rdev);
186 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
190 /* 1M ring buffer */ 187 /* 1M ring buffer */
191 r = r100_cp_init(rdev, 1024 * 1024); 188 r = r100_cp_init(rdev, 1024 * 1024);
192 if (r) { 189 if (r) {
@@ -221,6 +218,8 @@ int r520_resume(struct radeon_device *rdev)
221 atom_asic_init(rdev->mode_info.atom_context); 218 atom_asic_init(rdev->mode_info.atom_context);
222 /* Resume clock after posting */ 219 /* Resume clock after posting */
223 rv515_clock_startup(rdev); 220 rv515_clock_startup(rdev);
221 /* Initialize surface registers */
222 radeon_surface_init(rdev);
224 return r520_startup(rdev); 223 return r520_startup(rdev);
225} 224}
226 225
@@ -254,6 +253,9 @@ int r520_init(struct radeon_device *rdev)
254 RREG32(R_0007C0_CP_STAT)); 253 RREG32(R_0007C0_CP_STAT));
255 } 254 }
256 /* check if cards are posted or not */ 255 /* check if cards are posted or not */
256 if (radeon_boot_test_post_card(rdev) == false)
257 return -EINVAL;
258
257 if (!radeon_card_posted(rdev) && rdev->bios) { 259 if (!radeon_card_posted(rdev) && rdev->bios) {
258 DRM_INFO("GPU not posted. posting now...\n"); 260 DRM_INFO("GPU not posted. posting now...\n");
259 atom_asic_init(rdev->mode_info.atom_context); 261 atom_asic_init(rdev->mode_info.atom_context);
@@ -262,12 +264,15 @@ int r520_init(struct radeon_device *rdev)
262 radeon_get_clock_info(rdev->ddev); 264 radeon_get_clock_info(rdev->ddev);
263 /* Initialize power management */ 265 /* Initialize power management */
264 radeon_pm_init(rdev); 266 radeon_pm_init(rdev);
265 /* Get vram informations */ 267 /* initialize AGP */
266 r520_vram_info(rdev); 268 if (rdev->flags & RADEON_IS_AGP) {
267 /* Initialize memory controller (also test AGP) */ 269 r = radeon_agp_init(rdev);
268 r = r420_mc_init(rdev); 270 if (r) {
269 if (r) 271 radeon_agp_disable(rdev);
270 return r; 272 }
273 }
274 /* initialize memory controller */
275 r520_mc_init(rdev);
271 rv515_debugfs(rdev); 276 rv515_debugfs(rdev);
272 /* Fence driver */ 277 /* Fence driver */
273 r = radeon_fence_driver_init(rdev); 278 r = radeon_fence_driver_init(rdev);
@@ -277,7 +282,7 @@ int r520_init(struct radeon_device *rdev)
277 if (r) 282 if (r)
278 return r; 283 return r;
279 /* Memory manager */ 284 /* Memory manager */
280 r = radeon_object_init(rdev); 285 r = radeon_bo_init(rdev);
281 if (r) 286 if (r)
282 return r; 287 return r;
283 r = rv370_pcie_gart_init(rdev); 288 r = rv370_pcie_gart_init(rdev);
@@ -289,13 +294,12 @@ int r520_init(struct radeon_device *rdev)
289 if (r) { 294 if (r) {
290 /* Somethings want wront with the accel init stop accel */ 295 /* Somethings want wront with the accel init stop accel */
291 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 296 dev_err(rdev->dev, "Disabling GPU acceleration\n");
292 rv515_suspend(rdev);
293 r100_cp_fini(rdev); 297 r100_cp_fini(rdev);
294 r100_wb_fini(rdev); 298 r100_wb_fini(rdev);
295 r100_ib_fini(rdev); 299 r100_ib_fini(rdev);
300 radeon_irq_kms_fini(rdev);
296 rv370_pcie_gart_fini(rdev); 301 rv370_pcie_gart_fini(rdev);
297 radeon_agp_fini(rdev); 302 radeon_agp_fini(rdev);
298 radeon_irq_kms_fini(rdev);
299 rdev->accel_working = false; 303 rdev->accel_working = false;
300 } 304 }
301 return 0; 305 return 0;