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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/gpu/drm/radeon/r100_track.h
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/gpu/drm/radeon/r100_track.h')
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h22
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index f47cdca1c004..686f9dc5d4bd 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -46,19 +46,13 @@ struct r100_cs_track_texture {
46 unsigned height_11; 46 unsigned height_11;
47 bool use_pitch; 47 bool use_pitch;
48 bool enabled; 48 bool enabled;
49 bool lookup_disable;
49 bool roundup_w; 50 bool roundup_w;
50 bool roundup_h; 51 bool roundup_h;
51 unsigned compress_format; 52 unsigned compress_format;
52}; 53};
53 54
54struct r100_cs_track_limits {
55 unsigned num_cb;
56 unsigned num_texture;
57 unsigned max_levels;
58};
59
60struct r100_cs_track { 55struct r100_cs_track {
61 struct radeon_device *rdev;
62 unsigned num_cb; 56 unsigned num_cb;
63 unsigned num_texture; 57 unsigned num_texture;
64 unsigned maxy; 58 unsigned maxy;
@@ -69,14 +63,20 @@ struct r100_cs_track {
69 unsigned num_arrays; 63 unsigned num_arrays;
70 unsigned max_indx; 64 unsigned max_indx;
71 unsigned color_channel_mask; 65 unsigned color_channel_mask;
72 struct r100_cs_track_array arrays[11]; 66 struct r100_cs_track_array arrays[16];
73 struct r100_cs_track_cb cb[R300_MAX_CB]; 67 struct r100_cs_track_cb cb[R300_MAX_CB];
74 struct r100_cs_track_cb zb; 68 struct r100_cs_track_cb zb;
69 struct r100_cs_track_cb aa;
75 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 70 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
76 bool z_enabled; 71 bool z_enabled;
77 bool separate_cube; 72 bool separate_cube;
78 bool zb_cb_clear; 73 bool zb_cb_clear;
79 bool blend_read_enable; 74 bool blend_read_enable;
75 bool cb_dirty;
76 bool zb_dirty;
77 bool tex_dirty;
78 bool aa_dirty;
79 bool aaresolve;
80}; 80};
81 81
82int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 82int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
@@ -146,6 +146,12 @@ static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
146 ib = p->ib->ptr; 146 ib = p->ib->ptr;
147 track = (struct r100_cs_track *)p->track; 147 track = (struct r100_cs_track *)p->track;
148 c = radeon_get_ib_value(p, idx++) & 0x1F; 148 c = radeon_get_ib_value(p, idx++) & 0x1F;
149 if (c > 16) {
150 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
151 pkt->opcode);
152 r100_cs_dump_packet(p, pkt);
153 return -EINVAL;
154 }
149 track->num_arrays = c; 155 track->num_arrays = c;
150 for (i = 0; i < (c - 1); i+=2, idx+=3) { 156 for (i = 0; i < (c - 1); i+=2, idx+=3) {
151 r = r100_cs_packet_next_reloc(p, &reloc); 157 r = r100_cs_packet_next_reloc(p, &reloc);