Merge branch 'drm-next' of ../drm-next into drm-linus

conflict in radeon since new init path merged with vga arb code.

Conflicts:
	drivers/gpu/drm/radeon/radeon.h
	drivers/gpu/drm/radeon/radeon_asic.h
	drivers/gpu/drm/radeon/radeon_device.c

1 files changed, 269 insertions, 163 deletions

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e6cce24de802..161094c07d94 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -32,6 +32,9 @@
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "r100d.h"
+#include "rs100d.h"
+#include "rv200d.h"
+#include "rv250d.h"
 
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
@@ -60,18 +63,7 @@ MODULE_FIRMWARE(FIRMWARE_R520);
 
 /* This files gather functions specifics to:
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
- *
- * Some of these functions might be used by newer ASICs.
  */
-int r200_init(struct radeon_device *rdev);
-void r100_hdp_reset(struct radeon_device *rdev);
-void r100_gpu_init(struct radeon_device *rdev);
-int r100_gui_wait_for_idle(struct radeon_device *rdev);
-int r100_mc_wait_for_idle(struct radeon_device *rdev);
-void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
-void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
-int r100_debugfs_mc_info_init(struct radeon_device *rdev);
-
 
 /*
  * PCI GART
@@ -152,136 +144,6 @@ void r100_pci_gart_fini(struct radeon_device *rdev)
         radeon_gart_fini(rdev);
 }
 
-
-/*
- * MC
- */
-void r100_mc_disable_clients(struct radeon_device *rdev)
-{
-        uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
-
-        /* FIXME: is this function correct for rs100,rs200,rs300 ? */
-        if (r100_gui_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait GUI idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-
-        /* stop display and memory access */
-        ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
-        WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
-        crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
-        WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
-        crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
-
-        r100_gpu_wait_for_vsync(rdev);
-
-        WREG32(RADEON_CRTC_GEN_CNTL,
-               (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
-               RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
-
-        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
-                crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
-
-                r100_gpu_wait_for_vsync2(rdev);
-                WREG32(RADEON_CRTC2_GEN_CNTL,
-                       (crtc2_gen_cntl &
-                        ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
-                       RADEON_CRTC2_DISP_REQ_EN_B);
-        }
-
-        udelay(500);
-}
-
-void r100_mc_setup(struct radeon_device *rdev)
-{
-        uint32_t tmp;
-        int r;
-
-        r = r100_debugfs_mc_info_init(rdev);
-        if (r) {
-                DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
-        }
-        /* Write VRAM size in case we are limiting it */
-        WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
-        /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
-         * if the aperture is 64MB but we have 32MB VRAM
-         * we report only 32MB VRAM but we have to set MC_FB_LOCATION
-         * to 64MB, otherwise the gpu accidentially dies */
-        tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-        tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
-        tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
-        WREG32(RADEON_MC_FB_LOCATION, tmp);
-
-        /* Enable bus mastering */
-        tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
-        WREG32(RADEON_BUS_CNTL, tmp);
-
-        if (rdev->flags & RADEON_IS_AGP) {
-                tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
-                tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
-                tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
-                WREG32(RADEON_MC_AGP_LOCATION, tmp);
-                WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
-        } else {
-                WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
-                WREG32(RADEON_AGP_BASE, 0);
-        }
-
-        tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
-        tmp |= (7 << 28);
-        WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
-        (void)RREG32(RADEON_HOST_PATH_CNTL);
-        WREG32(RADEON_HOST_PATH_CNTL, tmp);
-        (void)RREG32(RADEON_HOST_PATH_CNTL);
-}
-
-int r100_mc_init(struct radeon_device *rdev)
-{
-        int r;
-
-        if (r100_debugfs_rbbm_init(rdev)) {
-                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
-        }
-
-        r100_gpu_init(rdev);
-        /* Disable gart which also disable out of gart access */
-        r100_pci_gart_disable(rdev);
-
-        /* Setup GPU memory space */
-        rdev->mc.gtt_location = 0xFFFFFFFFUL;
-        if (rdev->flags & RADEON_IS_AGP) {
-                r = radeon_agp_init(rdev);
-                if (r) {
-                        printk(KERN_WARNING "[drm] Disabling AGP\n");
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
-                } else {
-                        rdev->mc.gtt_location = rdev->mc.agp_base;
-                }
-        }
-        r = radeon_mc_setup(rdev);
-        if (r) {
-                return r;
-        }
-
-        r100_mc_disable_clients(rdev);
-        if (r100_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait MC idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-
-        r100_mc_setup(rdev);
-        return 0;
-}
-
-void r100_mc_fini(struct radeon_device *rdev)
-{
-}
-
-
-/*
- * Interrupts
- */
 int r100_irq_set(struct radeon_device *rdev)
 {
         uint32_t tmp = 0;
@@ -358,10 +220,6 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 }
 
-
-/*
- * Fence emission
- */
 void r100_fence_ring_emit(struct radeon_device *rdev,
                           struct radeon_fence *fence)
 {
@@ -377,10 +235,6 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 }
 
-
-/*
- * Writeback
- */
 int r100_wb_init(struct radeon_device *rdev)
 {
         int r;
@@ -504,10 +358,6 @@ int r100_copy_blit(struct radeon_device *rdev,
         return r;
 }
 
-
-/*
- * CP
- */
 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 {
         unsigned i;
@@ -612,6 +462,7 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
         }
         return err;
 }
+
 static void r100_cp_load_microcode(struct radeon_device *rdev)
 {
         const __be32 *fw_data;
@@ -978,7 +829,7 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 5);
-        reg = header >> 2;
+        reg = CP_PACKET0_GET_REG(header);
         mutex_lock(&p->rdev->ddev->mode_config.mutex);
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
@@ -1990,7 +1841,7 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
         r100_pll_errata_after_data(rdev);
 }
 
-int r100_init(struct radeon_device *rdev)
+void r100_set_safe_registers(struct radeon_device *rdev)
 {
         if (ASIC_IS_RN50(rdev)) {
                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
@@ -1999,9 +1850,8 @@ int r100_init(struct radeon_device *rdev)
                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
         } else {
-                return r200_init(rdev);
+                r200_set_safe_registers(rdev);
         }
-        return 0;
 }
 
 /*
@@ -2299,9 +2149,11 @@ void r100_bandwidth_update(struct radeon_device *rdev)
                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
         }
-        if (rdev->mode_info.crtcs[1]->base.enabled) {
-                mode2 = &rdev->mode_info.crtcs[1]->base.mode;
-                pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
+        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+                if (rdev->mode_info.crtcs[1]->base.enabled) {
+                        mode2 = &rdev->mode_info.crtcs[1]->base.mode;
+                        pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
+                }
         }
 
         min_mem_eff.full = rfixed_const_8(0);
@@ -3114,7 +2966,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
         WREG32(R_000740_CP_CSQ_CNTL, 0);
 
         /* Save few CRTC registers */
-        save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
+        save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
@@ -3124,7 +2976,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
         }
 
         /* Disable VGA aperture access */
-        WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
         /* Disable cursor, overlay, crtc */
         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
@@ -3156,10 +3008,264 @@ void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
                                 rdev->mc.vram_location);
         }
         /* Restore CRTC registers */
-        WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
         }
 }
+
+void r100_vga_render_disable(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        tmp = RREG8(R_0003C2_GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
+}
+
+static void r100_debugfs(struct radeon_device *rdev)
+{
+        int r;
+
+        r = r100_debugfs_mc_info_init(rdev);
+        if (r)
+                dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
+}
+
+static void r100_mc_program(struct radeon_device *rdev)
+{
+        struct r100_mc_save save;
+
+        /* Stops all mc clients */
+        r100_mc_stop(rdev, &save);
+        if (rdev->flags & RADEON_IS_AGP) {
+                WREG32(R_00014C_MC_AGP_LOCATION,
+                        S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
+                        S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
+                WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
+                if (rdev->family > CHIP_RV200)
+                        WREG32(R_00015C_AGP_BASE_2,
+                                upper_32_bits(rdev->mc.agp_base) & 0xff);
+        } else {
+                WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
+                WREG32(R_000170_AGP_BASE, 0);
+                if (rdev->family > CHIP_RV200)
+                        WREG32(R_00015C_AGP_BASE_2, 0);
+        }
+        /* Wait for mc idle */
+        if (r100_mc_wait_for_idle(rdev))
+                dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
+        /* Program MC, should be a 32bits limited address space */
+        WREG32(R_000148_MC_FB_LOCATION,
+                S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
+                S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
+        r100_mc_resume(rdev, &save);
+}
+
+void r100_clock_startup(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (radeon_dynclks != -1 && radeon_dynclks)
+                radeon_legacy_set_clock_gating(rdev, 1);
+        /* We need to force on some of the block */
+        tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
+        tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
+        if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
+                tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
+        WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
+}
+
+static int r100_startup(struct radeon_device *rdev)
+{
+        int r;
+
+        r100_mc_program(rdev);
+        /* Resume clock */
+        r100_clock_startup(rdev);
+        /* Initialize GPU configuration (# pipes, ...) */
+        r100_gpu_init(rdev);
+        /* Initialize GART (initialize after TTM so we can allocate
+         * memory through TTM but finalize after TTM) */
+        if (rdev->flags & RADEON_IS_PCI) {
+                r = r100_pci_gart_enable(rdev);
+                if (r)
+                        return r;
+        }
+        /* Enable IRQ */
+        rdev->irq.sw_int = true;
+        r100_irq_set(rdev);
+        /* 1M ring buffer */
+        r = r100_cp_init(rdev, 1024 * 1024);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
+                return r;
+        }
+        r = r100_wb_init(rdev);
+        if (r)
+                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
+        r = r100_ib_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
+                return r;
+        }
+        return 0;
+}
+
+int r100_resume(struct radeon_device *rdev)
+{
+        /* Make sur GART are not working */
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_disable(rdev);
+        /* Resume clock before doing reset */
+        r100_clock_startup(rdev);
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* post */
+        radeon_combios_asic_init(rdev->ddev);
+        /* Resume clock after posting */
+        r100_clock_startup(rdev);
+        return r100_startup(rdev);
+}
+
+int r100_suspend(struct radeon_device *rdev)
+{
+        r100_cp_disable(rdev);
+        r100_wb_disable(rdev);
+        r100_irq_disable(rdev);
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_disable(rdev);
+        return 0;
+}
+
+void r100_fini(struct radeon_device *rdev)
+{
+        r100_suspend(rdev);
+        r100_cp_fini(rdev);
+        r100_wb_fini(rdev);
+        r100_ib_fini(rdev);
+        radeon_gem_fini(rdev);
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_fini(rdev);
+        radeon_irq_kms_fini(rdev);
+        radeon_fence_driver_fini(rdev);
+        radeon_object_fini(rdev);
+        radeon_atombios_fini(rdev);
+        kfree(rdev->bios);
+        rdev->bios = NULL;
+}
+
+int r100_mc_init(struct radeon_device *rdev)
+{
+        int r;
+        u32 tmp;
+
+        /* Setup GPU memory space */
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        if (rdev->flags & RADEON_IS_IGP) {
+                tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
+                rdev->mc.vram_location = tmp << 16;
+        }
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r) {
+                        printk(KERN_WARNING "[drm] Disabling AGP\n");
+                        rdev->flags &= ~RADEON_IS_AGP;
+                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                } else {
+                        rdev->mc.gtt_location = rdev->mc.agp_base;
+                }
+        }
+        r = radeon_mc_setup(rdev);
+        if (r)
+                return r;
+        return 0;
+}
+
+int r100_init(struct radeon_device *rdev)
+{
+        int r;
+
+        /* Register debugfs file specific to this group of asics */
+        r100_debugfs(rdev);
+        /* Disable VGA */
+        r100_vga_render_disable(rdev);
+        /* Initialize scratch registers */
+        radeon_scratch_init(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
+        /* TODO: disable VGA need to use VGA request */
+        /* BIOS*/
+        if (!radeon_get_bios(rdev)) {
+                if (ASIC_IS_AVIVO(rdev))
+                        return -EINVAL;
+        }
+        if (rdev->is_atom_bios) {
+                dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
+                return -EINVAL;
+        } else {
+                r = radeon_combios_init(rdev);
+                if (r)
+                        return r;
+        }
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev,
+                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* check if cards are posted or not */
+        if (!radeon_card_posted(rdev) && rdev->bios) {
+                DRM_INFO("GPU not posted. posting now...\n");
+                radeon_combios_asic_init(rdev->ddev);
+        }
+        /* Set asic errata */
+        r100_errata(rdev);
+        /* Initialize clocks */
+        radeon_get_clock_info(rdev->ddev);
+        /* Get vram informations */
+        r100_vram_info(rdev);
+        /* Initialize memory controller (also test AGP) */
+        r = r100_mc_init(rdev);
+        if (r)
+                return r;
+        /* Fence driver */
+        r = radeon_fence_driver_init(rdev);
+        if (r)
+                return r;
+        r = radeon_irq_kms_init(rdev);
+        if (r)
+                return r;
+        /* Memory manager */
+        r = radeon_object_init(rdev);
+        if (r)
+                return r;
+        if (rdev->flags & RADEON_IS_PCI) {
+                r = r100_pci_gart_init(rdev);
+                if (r)
+                        return r;
+        }
+        r100_set_safe_registers(rdev);
+        rdev->accel_working = true;
+        r = r100_startup(rdev);
+        if (r) {
+                /* Somethings want wront with the accel init stop accel */
+                dev_err(rdev->dev, "Disabling GPU acceleration\n");
+                r100_suspend(rdev);
+                r100_cp_fini(rdev);
+                r100_wb_fini(rdev);
+                r100_ib_fini(rdev);
+                if (rdev->flags & RADEON_IS_PCI)
+                        r100_pci_gart_fini(rdev);
+                radeon_irq_kms_fini(rdev);
+                rdev->accel_working = false;
+        }
+        return 0;
+}