Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux

Pull drm merge (part 1) from Dave Airlie:
 "So first of all my tree and uapi stuff has a conflict mess, its my
  fault as the nouveau stuff didn't hit -next as were trying to rebase
  regressions out of it before we merged.

  Highlights:
   - SH mobile modesetting driver and associated helpers
   - some DRM core documentation
   - i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write
     combined pte writing, ilk rc6 support,
   - nouveau: major driver rework into a hw core driver, makes features
     like SLI a lot saner to implement,
   - psb: add eDP/DP support for Cedarview
   - radeon: 2 layer page tables, async VM pte updates, better PLL
     selection for > 2 screens, better ACPI interactions

  The rest is general grab bag of fixes.

  So why part 1? well I have the exynos pull req which came in a bit
  late but was waiting for me to do something they shouldn't have and it
  looks fairly safe, and David Howells has some more header cleanups
  he'd like me to pull, that seem like a good idea, but I'd like to get
  this merge out of the way so -next dosen't get blocked."

Tons of conflicts mostly due to silly include line changes, but mostly
mindless.  A few other small semantic conflicts too, noted from Dave's
pre-merged branch.

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits)
  drm/nv98/crypt: fix fuc build with latest envyas
  drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering
  drm/nv41/vm: fix and enable use of "real" pciegart
  drm/nv44/vm: fix and enable use of "real" pciegart
  drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie
  drm/nouveau: store supported dma mask in vmmgr
  drm/nvc0/ibus: initial implementation of subdev
  drm/nouveau/therm: add support for fan-control modes
  drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules
  drm/nouveau/therm: calculate the pwm divisor on nv50+
  drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster
  drm/nouveau/therm: move thermal-related functions to the therm subdev
  drm/nouveau/bios: parse the pwm divisor from the perf table
  drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices
  drm/nouveau/therm: rework thermal table parsing
  drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table
  drm/nouveau: fix pm initialization order
  drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it
  drm/nouveau: log channel debug/error messages from client object rather than drm client
  drm/nouveau: have drm debugging macros build on top of core macros
  ...

1 files changed, 19 insertions, 77 deletions

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 3183a815f71c..376884f1bcd2 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -79,10 +79,12 @@ MODULE_FIRMWARE(FIRMWARE_R520);
  */
 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
 {
-        struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
         int i;
 
-        if (radeon_crtc->crtc_id == 0) {
+        if (crtc >= rdev->num_crtc)
+                return;
+
+        if (crtc == 0) {
                 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
                         for (i = 0; i < rdev->usec_timeout; i++) {
                                 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
@@ -697,9 +699,6 @@ int r100_irq_set(struct radeon_device *rdev)
         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
                 tmp |= RADEON_SW_INT_ENABLE;
         }
-        if (rdev->irq.gui_idle) {
-                tmp |= RADEON_GUI_IDLE_MASK;
-        }
         if (rdev->irq.crtc_vblank_int[0] ||
             atomic_read(&rdev->irq.pflip[0])) {
                 tmp |= RADEON_CRTC_VBLANK_MASK;
@@ -736,12 +735,6 @@ static uint32_t r100_irq_ack(struct radeon_device *rdev)
                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 
-        /* the interrupt works, but the status bit is permanently asserted */
-        if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
-                if (!rdev->irq.gui_idle_acked)
-                        irq_mask |= RADEON_GUI_IDLE_STAT;
-        }
-
         if (irqs) {
                 WREG32(RADEON_GEN_INT_STATUS, irqs);
         }
@@ -753,9 +746,6 @@ int r100_irq_process(struct radeon_device *rdev)
         uint32_t status, msi_rearm;
         bool queue_hotplug = false;
 
-        /* reset gui idle ack.  the status bit is broken */
-        rdev->irq.gui_idle_acked = false;
-
         status = r100_irq_ack(rdev);
         if (!status) {
                 return IRQ_NONE;
@@ -768,11 +758,6 @@ int r100_irq_process(struct radeon_device *rdev)
                 if (status & RADEON_SW_INT_TEST) {
                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
                 }
-                /* gui idle interrupt */
-                if (status & RADEON_GUI_IDLE_STAT) {
-                        rdev->irq.gui_idle_acked = true;
-                        wake_up(&rdev->irq.idle_queue);
-                }
                 /* Vertical blank interrupts */
                 if (status & RADEON_CRTC_VBLANK_STAT) {
                         if (rdev->irq.crtc_vblank_int[0]) {
@@ -802,8 +787,6 @@ int r100_irq_process(struct radeon_device *rdev)
                 }
                 status = r100_irq_ack(rdev);
         }
-        /* reset gui idle ack.  the status bit is broken */
-        rdev->irq.gui_idle_acked = false;
         if (queue_hotplug)
                 schedule_work(&rdev->hotplug_work);
         if (rdev->msi_enabled) {
@@ -2529,7 +2512,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
 /*
  * Global GPU functions
  */
-void r100_errata(struct radeon_device *rdev)
+static void r100_errata(struct radeon_device *rdev)
 {
         rdev->pll_errata = 0;
 
@@ -2544,51 +2527,7 @@ void r100_errata(struct radeon_device *rdev)
         }
 }
 
-/* Wait for vertical sync on primary CRTC */
-void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
-{
-        uint32_t crtc_gen_cntl, tmp;
-        int i;
-
-        crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
-        if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
-            !(crtc_gen_cntl & RADEON_CRTC_EN)) {
-                return;
-        }
-        /* Clear the CRTC_VBLANK_SAVE bit */
-        WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
-        for (i = 0; i < rdev->usec_timeout; i++) {
-                tmp = RREG32(RADEON_CRTC_STATUS);
-                if (tmp & RADEON_CRTC_VBLANK_SAVE) {
-                        return;
-                }
-                DRM_UDELAY(1);
-        }
-}
-
-/* Wait for vertical sync on secondary CRTC */
-void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
-{
-        uint32_t crtc2_gen_cntl, tmp;
-        int i;
-
-        crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
-        if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
-            !(crtc2_gen_cntl & RADEON_CRTC2_EN))
-                return;
-
-        /* Clear the CRTC_VBLANK_SAVE bit */
-        WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
-        for (i = 0; i < rdev->usec_timeout; i++) {
-                tmp = RREG32(RADEON_CRTC2_STATUS);
-                if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
-                        return;
-                }
-                DRM_UDELAY(1);
-        }
-}
-
-int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
+static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
 {
         unsigned i;
         uint32_t tmp;
@@ -2949,7 +2888,7 @@ void r100_vga_set_state(struct radeon_device *rdev, bool state)
         WREG32(RADEON_CONFIG_CNTL, temp);
 }
 
-void r100_mc_init(struct radeon_device *rdev)
+static void r100_mc_init(struct radeon_device *rdev)
 {
         u64 base;
 
@@ -3021,7 +2960,7 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
         r100_pll_errata_after_data(rdev);
 }
 
-void r100_set_safe_registers(struct radeon_device *rdev)
+static void r100_set_safe_registers(struct radeon_device *rdev)
 {
         if (ASIC_IS_RN50(rdev)) {
                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
@@ -3816,9 +3755,10 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
                 return r;
         }
         WREG32(scratch, 0xCAFEDEAD);
-        r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
+        r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
         if (r) {
-                return r;
+                DRM_ERROR("radeon: failed to get ib (%d).\n", r);
+                goto free_scratch;
         }
         ib.ptr[0] = PACKET0(scratch, 0);
         ib.ptr[1] = 0xDEADBEEF;
@@ -3831,13 +3771,13 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
         ib.length_dw = 8;
         r = radeon_ib_schedule(rdev, &ib, NULL);
         if (r) {
-                radeon_scratch_free(rdev, scratch);
-                radeon_ib_free(rdev, &ib);
-                return r;
+                DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
+                goto free_ib;
         }
         r = radeon_fence_wait(ib.fence, false);
         if (r) {
-                return r;
+                DRM_ERROR("radeon: fence wait failed (%d).\n", r);
+                goto free_ib;
         }
         for (i = 0; i < rdev->usec_timeout; i++) {
                 tmp = RREG32(scratch);
@@ -3853,8 +3793,10 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
                           scratch, tmp);
                 r = -EINVAL;
         }
-        radeon_scratch_free(rdev, scratch);
+free_ib:
         radeon_ib_free(rdev, &ib);
+free_scratch:
+        radeon_scratch_free(rdev, scratch);
         return r;
 }
 
@@ -3963,7 +3905,7 @@ static void r100_mc_program(struct radeon_device *rdev)
         r100_mc_resume(rdev, &save);
 }
 
-void r100_clock_startup(struct radeon_device *rdev)
+static void r100_clock_startup(struct radeon_device *rdev)
 {
         u32 tmp;