drm/radeon: add spinlocks for indirect register accesss

This adds spinlocks to protect access to other
indirect register apertures.  These indirect spaces are
used pretty infrequently and we haven't had an reported
problems, but better safe than sorry.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 9fc61dd68bc0..24175717307b 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2853,21 +2853,28 @@ static void r100_pll_errata_after_data(struct radeon_device *rdev)
 
 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
 {
+        unsigned long flags;
         uint32_t data;
 
+        spin_lock_irqsave(&rdev->pll_idx_lock, flags);
         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
         r100_pll_errata_after_index(rdev);
         data = RREG32(RADEON_CLOCK_CNTL_DATA);
         r100_pll_errata_after_data(rdev);
+        spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
         return data;
 }
 
 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
+        unsigned long flags;
+
+        spin_lock_irqsave(&rdev->pll_idx_lock, flags);
         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
         r100_pll_errata_after_index(rdev);
         WREG32(RADEON_CLOCK_CNTL_DATA, v);
         r100_pll_errata_after_data(rdev);
+        spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
 }
 
 static void r100_set_safe_registers(struct radeon_device *rdev)