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authorChristian König <christian.koenig@amd.com>2013-10-30 11:51:09 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-11-01 15:25:52 -0400
commit24c164393dd2fa1c1fb51d5fec2f50bd6b7c037b (patch)
tree4eb520dad2e03ef9a0f189696e3907c0d3a8fbef /drivers/gpu/drm/radeon/ni.c
parent74d360f66b99231ed7007eb197dd18cda72c961c (diff)
drm/radeon: drop CP page table updates & cleanup v2
The DMA ring seems to be stable now. v2: remove pt_ring_index as well Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c76
1 files changed, 0 insertions, 76 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 93c1f9ef5da9..e299a38e683a 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -174,11 +174,6 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174extern void evergreen_program_aspm(struct radeon_device *rdev); 174extern void evergreen_program_aspm(struct radeon_device *rdev);
175extern void sumo_rlc_fini(struct radeon_device *rdev); 175extern void sumo_rlc_fini(struct radeon_device *rdev);
176extern int sumo_rlc_init(struct radeon_device *rdev); 176extern int sumo_rlc_init(struct radeon_device *rdev);
177extern void cayman_dma_vm_set_page(struct radeon_device *rdev,
178 struct radeon_ib *ib,
179 uint64_t pe,
180 uint64_t addr, unsigned count,
181 uint32_t incr, uint32_t flags);
182 177
183/* Firmware Names */ 178/* Firmware Names */
184MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 179MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
@@ -2399,77 +2394,6 @@ void cayman_vm_decode_fault(struct radeon_device *rdev,
2399 block, mc_id); 2394 block, mc_id);
2400} 2395}
2401 2396
2402#define R600_ENTRY_VALID (1 << 0)
2403#define R600_PTE_SYSTEM (1 << 1)
2404#define R600_PTE_SNOOPED (1 << 2)
2405#define R600_PTE_READABLE (1 << 5)
2406#define R600_PTE_WRITEABLE (1 << 6)
2407
2408uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
2409{
2410 uint32_t r600_flags = 0;
2411 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
2412 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
2413 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
2414 if (flags & RADEON_VM_PAGE_SYSTEM) {
2415 r600_flags |= R600_PTE_SYSTEM;
2416 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
2417 }
2418 return r600_flags;
2419}
2420
2421/**
2422 * cayman_vm_set_page - update the page tables using the CP
2423 *
2424 * @rdev: radeon_device pointer
2425 * @ib: indirect buffer to fill with commands
2426 * @pe: addr of the page entry
2427 * @addr: dst addr to write into pe
2428 * @count: number of page entries to update
2429 * @incr: increase next addr by incr bytes
2430 * @flags: access flags
2431 *
2432 * Update the page tables using the CP (cayman/TN).
2433 */
2434void cayman_vm_set_page(struct radeon_device *rdev,
2435 struct radeon_ib *ib,
2436 uint64_t pe,
2437 uint64_t addr, unsigned count,
2438 uint32_t incr, uint32_t flags)
2439{
2440 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
2441 uint64_t value;
2442 unsigned ndw;
2443
2444 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
2445 while (count) {
2446 ndw = 1 + count * 2;
2447 if (ndw > 0x3FFF)
2448 ndw = 0x3FFF;
2449
2450 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
2451 ib->ptr[ib->length_dw++] = pe;
2452 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2453 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
2454 if (flags & RADEON_VM_PAGE_SYSTEM) {
2455 value = radeon_vm_map_gart(rdev, addr);
2456 value &= 0xFFFFFFFFFFFFF000ULL;
2457 } else if (flags & RADEON_VM_PAGE_VALID) {
2458 value = addr;
2459 } else {
2460 value = 0;
2461 }
2462 addr += incr;
2463 value |= r600_flags;
2464 ib->ptr[ib->length_dw++] = value;
2465 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2466 }
2467 }
2468 } else {
2469 cayman_dma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
2470 }
2471}
2472
2473/** 2397/**
2474 * cayman_vm_flush - vm flush using the CP 2398 * cayman_vm_flush - vm flush using the CP
2475 * 2399 *