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authorPaul Mundt <lethal@linux-sh.org>2010-07-05 02:46:08 -0400
committerPaul Mundt <lethal@linux-sh.org>2010-07-05 02:46:08 -0400
commit285eba57db7bd7d7c3c5929fb8621fdcaaea1b00 (patch)
treea9e7f0563cef296b24c53b20dbb388ec5c210172 /drivers/gpu/drm/radeon/evergreend.h
parent1c14e6cecb1811543b1016f27e5d308fbea8c08a (diff)
parent815c4163b6c8ebf8152f42b0a5fd015cfdcedc78 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: include/linux/serial_sci.h Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h467
1 files changed, 467 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 93e9e17ad54a..a1cd621780e2 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -218,6 +218,8 @@
218#define CLIP_VTX_REORDER_ENA (1 << 0) 218#define CLIP_VTX_REORDER_ENA (1 << 0)
219#define NUM_CLIP_SEQ(x) ((x) << 1) 219#define NUM_CLIP_SEQ(x) ((x) << 1)
220#define PA_SC_AA_CONFIG 0x28C04 220#define PA_SC_AA_CONFIG 0x28C04
221#define MSAA_NUM_SAMPLES_SHIFT 0
222#define MSAA_NUM_SAMPLES_MASK 0x3
221#define PA_SC_CLIPRECT_RULE 0x2820C 223#define PA_SC_CLIPRECT_RULE 0x2820C
222#define PA_SC_EDGERULE 0x28230 224#define PA_SC_EDGERULE 0x28230
223#define PA_SC_FIFO_SIZE 0x8BCC 225#define PA_SC_FIFO_SIZE 0x8BCC
@@ -553,4 +555,469 @@
553# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 555# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
554# define DC_HPDx_EN (1 << 28) 556# define DC_HPDx_EN (1 << 28)
555 557
558/*
559 * PM4
560 */
561#define PACKET_TYPE0 0
562#define PACKET_TYPE1 1
563#define PACKET_TYPE2 2
564#define PACKET_TYPE3 3
565
566#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
567#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
568#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
569#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
570#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
571 (((reg) >> 2) & 0xFFFF) | \
572 ((n) & 0x3FFF) << 16)
573#define CP_PACKET2 0x80000000
574#define PACKET2_PAD_SHIFT 0
575#define PACKET2_PAD_MASK (0x3fffffff << 0)
576
577#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
578
579#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
580 (((op) & 0xFF) << 8) | \
581 ((n) & 0x3FFF) << 16)
582
583/* Packet 3 types */
584#define PACKET3_NOP 0x10
585#define PACKET3_SET_BASE 0x11
586#define PACKET3_CLEAR_STATE 0x12
587#define PACKET3_INDIRECT_BUFFER_SIZE 0x13
588#define PACKET3_DISPATCH_DIRECT 0x15
589#define PACKET3_DISPATCH_INDIRECT 0x16
590#define PACKET3_INDIRECT_BUFFER_END 0x17
591#define PACKET3_SET_PREDICATION 0x20
592#define PACKET3_REG_RMW 0x21
593#define PACKET3_COND_EXEC 0x22
594#define PACKET3_PRED_EXEC 0x23
595#define PACKET3_DRAW_INDIRECT 0x24
596#define PACKET3_DRAW_INDEX_INDIRECT 0x25
597#define PACKET3_INDEX_BASE 0x26
598#define PACKET3_DRAW_INDEX_2 0x27
599#define PACKET3_CONTEXT_CONTROL 0x28
600#define PACKET3_DRAW_INDEX_OFFSET 0x29
601#define PACKET3_INDEX_TYPE 0x2A
602#define PACKET3_DRAW_INDEX 0x2B
603#define PACKET3_DRAW_INDEX_AUTO 0x2D
604#define PACKET3_DRAW_INDEX_IMMD 0x2E
605#define PACKET3_NUM_INSTANCES 0x2F
606#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
607#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
608#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
609#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
610#define PACKET3_MEM_SEMAPHORE 0x39
611#define PACKET3_MPEG_INDEX 0x3A
612#define PACKET3_WAIT_REG_MEM 0x3C
613#define PACKET3_MEM_WRITE 0x3D
614#define PACKET3_INDIRECT_BUFFER 0x32
615#define PACKET3_SURFACE_SYNC 0x43
616# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
617# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
618# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
619# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
620# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
621# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
622# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
623# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
624# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
625# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
626# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
627# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
628# define PACKET3_CB11_DEST_BASE_ENA (1 << 17)
629# define PACKET3_FULL_CACHE_ENA (1 << 20)
630# define PACKET3_TC_ACTION_ENA (1 << 23)
631# define PACKET3_VC_ACTION_ENA (1 << 24)
632# define PACKET3_CB_ACTION_ENA (1 << 25)
633# define PACKET3_DB_ACTION_ENA (1 << 26)
634# define PACKET3_SH_ACTION_ENA (1 << 27)
635# define PACKET3_SMX_ACTION_ENA (1 << 28)
636#define PACKET3_ME_INITIALIZE 0x44
637#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
638#define PACKET3_COND_WRITE 0x45
639#define PACKET3_EVENT_WRITE 0x46
640#define PACKET3_EVENT_WRITE_EOP 0x47
641#define PACKET3_EVENT_WRITE_EOS 0x48
642#define PACKET3_PREAMBLE_CNTL 0x4A
643#define PACKET3_RB_OFFSET 0x4B
644#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
645#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
646#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
647#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
648#define PACKET3_ONE_REG_WRITE 0x57
649#define PACKET3_SET_CONFIG_REG 0x68
650#define PACKET3_SET_CONFIG_REG_START 0x00008000
651#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
652#define PACKET3_SET_CONTEXT_REG 0x69
653#define PACKET3_SET_CONTEXT_REG_START 0x00028000
654#define PACKET3_SET_CONTEXT_REG_END 0x00029000
655#define PACKET3_SET_ALU_CONST 0x6A
656/* alu const buffers only; no reg file */
657#define PACKET3_SET_BOOL_CONST 0x6B
658#define PACKET3_SET_BOOL_CONST_START 0x0003a500
659#define PACKET3_SET_BOOL_CONST_END 0x0003a518
660#define PACKET3_SET_LOOP_CONST 0x6C
661#define PACKET3_SET_LOOP_CONST_START 0x0003a200
662#define PACKET3_SET_LOOP_CONST_END 0x0003a500
663#define PACKET3_SET_RESOURCE 0x6D
664#define PACKET3_SET_RESOURCE_START 0x00030000
665#define PACKET3_SET_RESOURCE_END 0x00038000
666#define PACKET3_SET_SAMPLER 0x6E
667#define PACKET3_SET_SAMPLER_START 0x0003c000
668#define PACKET3_SET_SAMPLER_END 0x0003c600
669#define PACKET3_SET_CTL_CONST 0x6F
670#define PACKET3_SET_CTL_CONST_START 0x0003cff0
671#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
672#define PACKET3_SET_RESOURCE_OFFSET 0x70
673#define PACKET3_SET_ALU_CONST_VS 0x71
674#define PACKET3_SET_ALU_CONST_DI 0x72
675#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
676#define PACKET3_SET_RESOURCE_INDIRECT 0x74
677#define PACKET3_SET_APPEND_CNT 0x75
678
679#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
680#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
681#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
682#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
683#define SQ_TEX_VTX_INVALID_BUFFER 0x1
684#define SQ_TEX_VTX_VALID_TEXTURE 0x2
685#define SQ_TEX_VTX_VALID_BUFFER 0x3
686
687#define SQ_CONST_MEM_BASE 0x8df8
688
689#define SQ_ESGS_RING_SIZE 0x8c44
690#define SQ_GSVS_RING_SIZE 0x8c4c
691#define SQ_ESTMP_RING_SIZE 0x8c54
692#define SQ_GSTMP_RING_SIZE 0x8c5c
693#define SQ_VSTMP_RING_SIZE 0x8c64
694#define SQ_PSTMP_RING_SIZE 0x8c6c
695#define SQ_LSTMP_RING_SIZE 0x8e14
696#define SQ_HSTMP_RING_SIZE 0x8e1c
697#define VGT_TF_RING_SIZE 0x8988
698
699#define SQ_ESGS_RING_ITEMSIZE 0x28900
700#define SQ_GSVS_RING_ITEMSIZE 0x28904
701#define SQ_ESTMP_RING_ITEMSIZE 0x28908
702#define SQ_GSTMP_RING_ITEMSIZE 0x2890c
703#define SQ_VSTMP_RING_ITEMSIZE 0x28910
704#define SQ_PSTMP_RING_ITEMSIZE 0x28914
705#define SQ_LSTMP_RING_ITEMSIZE 0x28830
706#define SQ_HSTMP_RING_ITEMSIZE 0x28834
707
708#define SQ_GS_VERT_ITEMSIZE 0x2891c
709#define SQ_GS_VERT_ITEMSIZE_1 0x28920
710#define SQ_GS_VERT_ITEMSIZE_2 0x28924
711#define SQ_GS_VERT_ITEMSIZE_3 0x28928
712#define SQ_GSVS_RING_OFFSET_1 0x2892c
713#define SQ_GSVS_RING_OFFSET_2 0x28930
714#define SQ_GSVS_RING_OFFSET_3 0x28934
715
716#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
717#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
718
719#define SQ_ALU_CONST_CACHE_PS_0 0x28940
720#define SQ_ALU_CONST_CACHE_PS_1 0x28944
721#define SQ_ALU_CONST_CACHE_PS_2 0x28948
722#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
723#define SQ_ALU_CONST_CACHE_PS_4 0x28950
724#define SQ_ALU_CONST_CACHE_PS_5 0x28954
725#define SQ_ALU_CONST_CACHE_PS_6 0x28958
726#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
727#define SQ_ALU_CONST_CACHE_PS_8 0x28960
728#define SQ_ALU_CONST_CACHE_PS_9 0x28964
729#define SQ_ALU_CONST_CACHE_PS_10 0x28968
730#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
731#define SQ_ALU_CONST_CACHE_PS_12 0x28970
732#define SQ_ALU_CONST_CACHE_PS_13 0x28974
733#define SQ_ALU_CONST_CACHE_PS_14 0x28978
734#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
735#define SQ_ALU_CONST_CACHE_VS_0 0x28980
736#define SQ_ALU_CONST_CACHE_VS_1 0x28984
737#define SQ_ALU_CONST_CACHE_VS_2 0x28988
738#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
739#define SQ_ALU_CONST_CACHE_VS_4 0x28990
740#define SQ_ALU_CONST_CACHE_VS_5 0x28994
741#define SQ_ALU_CONST_CACHE_VS_6 0x28998
742#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
743#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
744#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
745#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
746#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
747#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
748#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
749#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
750#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
751#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
752#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
753#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
754#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
755#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
756#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
757#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
758#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
759#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
760#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
761#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
762#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
763#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
764#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
765#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
766#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
767#define SQ_ALU_CONST_CACHE_HS_0 0x28f00
768#define SQ_ALU_CONST_CACHE_HS_1 0x28f04
769#define SQ_ALU_CONST_CACHE_HS_2 0x28f08
770#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
771#define SQ_ALU_CONST_CACHE_HS_4 0x28f10
772#define SQ_ALU_CONST_CACHE_HS_5 0x28f14
773#define SQ_ALU_CONST_CACHE_HS_6 0x28f18
774#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
775#define SQ_ALU_CONST_CACHE_HS_8 0x28f20
776#define SQ_ALU_CONST_CACHE_HS_9 0x28f24
777#define SQ_ALU_CONST_CACHE_HS_10 0x28f28
778#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
779#define SQ_ALU_CONST_CACHE_HS_12 0x28f30
780#define SQ_ALU_CONST_CACHE_HS_13 0x28f34
781#define SQ_ALU_CONST_CACHE_HS_14 0x28f38
782#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
783#define SQ_ALU_CONST_CACHE_LS_0 0x28f40
784#define SQ_ALU_CONST_CACHE_LS_1 0x28f44
785#define SQ_ALU_CONST_CACHE_LS_2 0x28f48
786#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
787#define SQ_ALU_CONST_CACHE_LS_4 0x28f50
788#define SQ_ALU_CONST_CACHE_LS_5 0x28f54
789#define SQ_ALU_CONST_CACHE_LS_6 0x28f58
790#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
791#define SQ_ALU_CONST_CACHE_LS_8 0x28f60
792#define SQ_ALU_CONST_CACHE_LS_9 0x28f64
793#define SQ_ALU_CONST_CACHE_LS_10 0x28f68
794#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
795#define SQ_ALU_CONST_CACHE_LS_12 0x28f70
796#define SQ_ALU_CONST_CACHE_LS_13 0x28f74
797#define SQ_ALU_CONST_CACHE_LS_14 0x28f78
798#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
799
800#define DB_DEPTH_CONTROL 0x28800
801#define DB_DEPTH_VIEW 0x28008
802#define DB_HTILE_DATA_BASE 0x28014
803#define DB_Z_INFO 0x28040
804# define Z_ARRAY_MODE(x) ((x) << 4)
805#define DB_STENCIL_INFO 0x28044
806#define DB_Z_READ_BASE 0x28048
807#define DB_STENCIL_READ_BASE 0x2804c
808#define DB_Z_WRITE_BASE 0x28050
809#define DB_STENCIL_WRITE_BASE 0x28054
810#define DB_DEPTH_SIZE 0x28058
811
812#define SQ_PGM_START_PS 0x28840
813#define SQ_PGM_START_VS 0x2885c
814#define SQ_PGM_START_GS 0x28874
815#define SQ_PGM_START_ES 0x2888c
816#define SQ_PGM_START_FS 0x288a4
817#define SQ_PGM_START_HS 0x288b8
818#define SQ_PGM_START_LS 0x288d0
819
820#define VGT_STRMOUT_CONFIG 0x28b94
821#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
822
823#define CB_TARGET_MASK 0x28238
824#define CB_SHADER_MASK 0x2823c
825
826#define GDS_ADDR_BASE 0x28720
827
828#define CB_IMMED0_BASE 0x28b9c
829#define CB_IMMED1_BASE 0x28ba0
830#define CB_IMMED2_BASE 0x28ba4
831#define CB_IMMED3_BASE 0x28ba8
832#define CB_IMMED4_BASE 0x28bac
833#define CB_IMMED5_BASE 0x28bb0
834#define CB_IMMED6_BASE 0x28bb4
835#define CB_IMMED7_BASE 0x28bb8
836#define CB_IMMED8_BASE 0x28bbc
837#define CB_IMMED9_BASE 0x28bc0
838#define CB_IMMED10_BASE 0x28bc4
839#define CB_IMMED11_BASE 0x28bc8
840
841/* all 12 CB blocks have these regs */
842#define CB_COLOR0_BASE 0x28c60
843#define CB_COLOR0_PITCH 0x28c64
844#define CB_COLOR0_SLICE 0x28c68
845#define CB_COLOR0_VIEW 0x28c6c
846#define CB_COLOR0_INFO 0x28c70
847# define CB_ARRAY_MODE(x) ((x) << 8)
848# define ARRAY_LINEAR_GENERAL 0
849# define ARRAY_LINEAR_ALIGNED 1
850# define ARRAY_1D_TILED_THIN1 2
851# define ARRAY_2D_TILED_THIN1 4
852#define CB_COLOR0_ATTRIB 0x28c74
853#define CB_COLOR0_DIM 0x28c78
854/* only CB0-7 blocks have these regs */
855#define CB_COLOR0_CMASK 0x28c7c
856#define CB_COLOR0_CMASK_SLICE 0x28c80
857#define CB_COLOR0_FMASK 0x28c84
858#define CB_COLOR0_FMASK_SLICE 0x28c88
859#define CB_COLOR0_CLEAR_WORD0 0x28c8c
860#define CB_COLOR0_CLEAR_WORD1 0x28c90
861#define CB_COLOR0_CLEAR_WORD2 0x28c94
862#define CB_COLOR0_CLEAR_WORD3 0x28c98
863
864#define CB_COLOR1_BASE 0x28c9c
865#define CB_COLOR2_BASE 0x28cd8
866#define CB_COLOR3_BASE 0x28d14
867#define CB_COLOR4_BASE 0x28d50
868#define CB_COLOR5_BASE 0x28d8c
869#define CB_COLOR6_BASE 0x28dc8
870#define CB_COLOR7_BASE 0x28e04
871#define CB_COLOR8_BASE 0x28e40
872#define CB_COLOR9_BASE 0x28e5c
873#define CB_COLOR10_BASE 0x28e78
874#define CB_COLOR11_BASE 0x28e94
875
876#define CB_COLOR1_PITCH 0x28ca0
877#define CB_COLOR2_PITCH 0x28cdc
878#define CB_COLOR3_PITCH 0x28d18
879#define CB_COLOR4_PITCH 0x28d54
880#define CB_COLOR5_PITCH 0x28d90
881#define CB_COLOR6_PITCH 0x28dcc
882#define CB_COLOR7_PITCH 0x28e08
883#define CB_COLOR8_PITCH 0x28e44
884#define CB_COLOR9_PITCH 0x28e60
885#define CB_COLOR10_PITCH 0x28e7c
886#define CB_COLOR11_PITCH 0x28e98
887
888#define CB_COLOR1_SLICE 0x28ca4
889#define CB_COLOR2_SLICE 0x28ce0
890#define CB_COLOR3_SLICE 0x28d1c
891#define CB_COLOR4_SLICE 0x28d58
892#define CB_COLOR5_SLICE 0x28d94
893#define CB_COLOR6_SLICE 0x28dd0
894#define CB_COLOR7_SLICE 0x28e0c
895#define CB_COLOR8_SLICE 0x28e48
896#define CB_COLOR9_SLICE 0x28e64
897#define CB_COLOR10_SLICE 0x28e80
898#define CB_COLOR11_SLICE 0x28e9c
899
900#define CB_COLOR1_VIEW 0x28ca8
901#define CB_COLOR2_VIEW 0x28ce4
902#define CB_COLOR3_VIEW 0x28d20
903#define CB_COLOR4_VIEW 0x28d5c
904#define CB_COLOR5_VIEW 0x28d98
905#define CB_COLOR6_VIEW 0x28dd4
906#define CB_COLOR7_VIEW 0x28e10
907#define CB_COLOR8_VIEW 0x28e4c
908#define CB_COLOR9_VIEW 0x28e68
909#define CB_COLOR10_VIEW 0x28e84
910#define CB_COLOR11_VIEW 0x28ea0
911
912#define CB_COLOR1_INFO 0x28cac
913#define CB_COLOR2_INFO 0x28ce8
914#define CB_COLOR3_INFO 0x28d24
915#define CB_COLOR4_INFO 0x28d60
916#define CB_COLOR5_INFO 0x28d9c
917#define CB_COLOR6_INFO 0x28dd8
918#define CB_COLOR7_INFO 0x28e14
919#define CB_COLOR8_INFO 0x28e50
920#define CB_COLOR9_INFO 0x28e6c
921#define CB_COLOR10_INFO 0x28e88
922#define CB_COLOR11_INFO 0x28ea4
923
924#define CB_COLOR1_ATTRIB 0x28cb0
925#define CB_COLOR2_ATTRIB 0x28cec
926#define CB_COLOR3_ATTRIB 0x28d28
927#define CB_COLOR4_ATTRIB 0x28d64
928#define CB_COLOR5_ATTRIB 0x28da0
929#define CB_COLOR6_ATTRIB 0x28ddc
930#define CB_COLOR7_ATTRIB 0x28e18
931#define CB_COLOR8_ATTRIB 0x28e54
932#define CB_COLOR9_ATTRIB 0x28e70
933#define CB_COLOR10_ATTRIB 0x28e8c
934#define CB_COLOR11_ATTRIB 0x28ea8
935
936#define CB_COLOR1_DIM 0x28cb4
937#define CB_COLOR2_DIM 0x28cf0
938#define CB_COLOR3_DIM 0x28d2c
939#define CB_COLOR4_DIM 0x28d68
940#define CB_COLOR5_DIM 0x28da4
941#define CB_COLOR6_DIM 0x28de0
942#define CB_COLOR7_DIM 0x28e1c
943#define CB_COLOR8_DIM 0x28e58
944#define CB_COLOR9_DIM 0x28e74
945#define CB_COLOR10_DIM 0x28e90
946#define CB_COLOR11_DIM 0x28eac
947
948#define CB_COLOR1_CMASK 0x28cb8
949#define CB_COLOR2_CMASK 0x28cf4
950#define CB_COLOR3_CMASK 0x28d30
951#define CB_COLOR4_CMASK 0x28d6c
952#define CB_COLOR5_CMASK 0x28da8
953#define CB_COLOR6_CMASK 0x28de4
954#define CB_COLOR7_CMASK 0x28e20
955
956#define CB_COLOR1_CMASK_SLICE 0x28cbc
957#define CB_COLOR2_CMASK_SLICE 0x28cf8
958#define CB_COLOR3_CMASK_SLICE 0x28d34
959#define CB_COLOR4_CMASK_SLICE 0x28d70
960#define CB_COLOR5_CMASK_SLICE 0x28dac
961#define CB_COLOR6_CMASK_SLICE 0x28de8
962#define CB_COLOR7_CMASK_SLICE 0x28e24
963
964#define CB_COLOR1_FMASK 0x28cc0
965#define CB_COLOR2_FMASK 0x28cfc
966#define CB_COLOR3_FMASK 0x28d38
967#define CB_COLOR4_FMASK 0x28d74
968#define CB_COLOR5_FMASK 0x28db0
969#define CB_COLOR6_FMASK 0x28dec
970#define CB_COLOR7_FMASK 0x28e28
971
972#define CB_COLOR1_FMASK_SLICE 0x28cc4
973#define CB_COLOR2_FMASK_SLICE 0x28d00
974#define CB_COLOR3_FMASK_SLICE 0x28d3c
975#define CB_COLOR4_FMASK_SLICE 0x28d78
976#define CB_COLOR5_FMASK_SLICE 0x28db4
977#define CB_COLOR6_FMASK_SLICE 0x28df0
978#define CB_COLOR7_FMASK_SLICE 0x28e2c
979
980#define CB_COLOR1_CLEAR_WORD0 0x28cc8
981#define CB_COLOR2_CLEAR_WORD0 0x28d04
982#define CB_COLOR3_CLEAR_WORD0 0x28d40
983#define CB_COLOR4_CLEAR_WORD0 0x28d7c
984#define CB_COLOR5_CLEAR_WORD0 0x28db8
985#define CB_COLOR6_CLEAR_WORD0 0x28df4
986#define CB_COLOR7_CLEAR_WORD0 0x28e30
987
988#define CB_COLOR1_CLEAR_WORD1 0x28ccc
989#define CB_COLOR2_CLEAR_WORD1 0x28d08
990#define CB_COLOR3_CLEAR_WORD1 0x28d44
991#define CB_COLOR4_CLEAR_WORD1 0x28d80
992#define CB_COLOR5_CLEAR_WORD1 0x28dbc
993#define CB_COLOR6_CLEAR_WORD1 0x28df8
994#define CB_COLOR7_CLEAR_WORD1 0x28e34
995
996#define CB_COLOR1_CLEAR_WORD2 0x28cd0
997#define CB_COLOR2_CLEAR_WORD2 0x28d0c
998#define CB_COLOR3_CLEAR_WORD2 0x28d48
999#define CB_COLOR4_CLEAR_WORD2 0x28d84
1000#define CB_COLOR5_CLEAR_WORD2 0x28dc0
1001#define CB_COLOR6_CLEAR_WORD2 0x28dfc
1002#define CB_COLOR7_CLEAR_WORD2 0x28e38
1003
1004#define CB_COLOR1_CLEAR_WORD3 0x28cd4
1005#define CB_COLOR2_CLEAR_WORD3 0x28d10
1006#define CB_COLOR3_CLEAR_WORD3 0x28d4c
1007#define CB_COLOR4_CLEAR_WORD3 0x28d88
1008#define CB_COLOR5_CLEAR_WORD3 0x28dc4
1009#define CB_COLOR6_CLEAR_WORD3 0x28e00
1010#define CB_COLOR7_CLEAR_WORD3 0x28e3c
1011
1012#define SQ_TEX_RESOURCE_WORD0_0 0x30000
1013#define SQ_TEX_RESOURCE_WORD1_0 0x30004
1014# define TEX_ARRAY_MODE(x) ((x) << 28)
1015#define SQ_TEX_RESOURCE_WORD2_0 0x30008
1016#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
1017#define SQ_TEX_RESOURCE_WORD4_0 0x30010
1018#define SQ_TEX_RESOURCE_WORD5_0 0x30014
1019#define SQ_TEX_RESOURCE_WORD6_0 0x30018
1020#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
1021
1022
556#endif 1023#endif