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authorTony Lindgren <tony@atomide.com>2012-11-13 16:25:38 -0500
committerTony Lindgren <tony@atomide.com>2012-11-13 16:25:38 -0500
commit89ab216b33ba9405880fd3d89531305a931bc70f (patch)
tree8f6428ce51ecaed6f6e1379c036dbe341eb71e34 /drivers/gpu/drm/radeon/evergreen_cs.c
parentc9d501e5cb0238910337213e12a09127221c35d8 (diff)
parent46bf4a562207c5ebd24e1dde5e5ee326cd3d6b91 (diff)
Merge branch 'omap-for-v3.8/pm' into omap-for-v3.8/clock
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_cs.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 573ed1bc6cf7..95e6318b6268 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -264,7 +264,7 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
264 /* macro tile width & height */ 264 /* macro tile width & height */
265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; 265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; 266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
267 mtileb = (palign / 8) * (halign / 8) * tileb;; 267 mtileb = (palign / 8) * (halign / 8) * tileb;
268 mtile_pr = surf->nbx / palign; 268 mtile_pr = surf->nbx / palign;
269 mtile_ps = (mtile_pr * surf->nby) / halign; 269 mtile_ps = (mtile_pr * surf->nby) / halign;
270 surf->layer_size = mtile_ps * mtileb * slice_pt; 270 surf->layer_size = mtile_ps * mtileb * slice_pt;
@@ -2829,6 +2829,7 @@ static bool evergreen_vm_reg_valid(u32 reg)
2829 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS: 2829 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
2830 return true; 2830 return true;
2831 default: 2831 default:
2832 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2832 return false; 2833 return false;
2833 } 2834 }
2834} 2835}