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authorAlex Deucher <alexdeucher@gmail.com>2011-06-08 15:26:45 -0400
committerDave Airlie <airlied@redhat.com>2011-06-20 22:36:39 -0400
commit033b5650010652c069494df58424c4b98412fe3b (patch)
treeb3a5204f19648d6e02821f29b4cf9817c2d6ca33 /drivers/gpu/drm/radeon/evergreen_cs.c
parent0d74f86f37306da8619eb049d88ab7ee523eec9c (diff)
drm/radeon/kms: add initial CS checker support for compute
- Add some new compute regs - Add new dispatch packets for evergreen/cayman Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_cs.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c57
1 files changed, 56 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 23d36417158d..189e86522b5b 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -856,7 +856,6 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
856 case SQ_PGM_START_PS: 856 case SQ_PGM_START_PS:
857 case SQ_PGM_START_HS: 857 case SQ_PGM_START_HS:
858 case SQ_PGM_START_LS: 858 case SQ_PGM_START_LS:
859 case GDS_ADDR_BASE:
860 case SQ_CONST_MEM_BASE: 859 case SQ_CONST_MEM_BASE:
861 case SQ_ALU_CONST_CACHE_GS_0: 860 case SQ_ALU_CONST_CACHE_GS_0:
862 case SQ_ALU_CONST_CACHE_GS_1: 861 case SQ_ALU_CONST_CACHE_GS_1:
@@ -946,6 +945,34 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
946 } 945 }
947 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 946 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
948 break; 947 break;
948 case SX_MEMORY_EXPORT_BASE:
949 if (p->rdev->family >= CHIP_CAYMAN) {
950 dev_warn(p->dev, "bad SET_CONFIG_REG "
951 "0x%04X\n", reg);
952 return -EINVAL;
953 }
954 r = evergreen_cs_packet_next_reloc(p, &reloc);
955 if (r) {
956 dev_warn(p->dev, "bad SET_CONFIG_REG "
957 "0x%04X\n", reg);
958 return -EINVAL;
959 }
960 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961 break;
962 case CAYMAN_SX_SCATTER_EXPORT_BASE:
963 if (p->rdev->family < CHIP_CAYMAN) {
964 dev_warn(p->dev, "bad SET_CONTEXT_REG "
965 "0x%04X\n", reg);
966 return -EINVAL;
967 }
968 r = evergreen_cs_packet_next_reloc(p, &reloc);
969 if (r) {
970 dev_warn(p->dev, "bad SET_CONTEXT_REG "
971 "0x%04X\n", reg);
972 return -EINVAL;
973 }
974 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
975 break;
949 default: 976 default:
950 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 977 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
951 return -EINVAL; 978 return -EINVAL;
@@ -1153,6 +1180,34 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
1153 return r; 1180 return r;
1154 } 1181 }
1155 break; 1182 break;
1183 case PACKET3_DISPATCH_DIRECT:
1184 if (pkt->count != 3) {
1185 DRM_ERROR("bad DISPATCH_DIRECT\n");
1186 return -EINVAL;
1187 }
1188 r = evergreen_cs_track_check(p);
1189 if (r) {
1190 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1191 return r;
1192 }
1193 break;
1194 case PACKET3_DISPATCH_INDIRECT:
1195 if (pkt->count != 1) {
1196 DRM_ERROR("bad DISPATCH_INDIRECT\n");
1197 return -EINVAL;
1198 }
1199 r = evergreen_cs_packet_next_reloc(p, &reloc);
1200 if (r) {
1201 DRM_ERROR("bad DISPATCH_INDIRECT\n");
1202 return -EINVAL;
1203 }
1204 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1205 r = evergreen_cs_track_check(p);
1206 if (r) {
1207 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1208 return r;
1209 }
1210 break;
1156 case PACKET3_WAIT_REG_MEM: 1211 case PACKET3_WAIT_REG_MEM:
1157 if (pkt->count != 5) { 1212 if (pkt->count != 5) {
1158 DRM_ERROR("bad WAIT_REG_MEM\n"); 1213 DRM_ERROR("bad WAIT_REG_MEM\n");