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authorOlof Johansson <olof@lixom.net>2014-11-04 23:37:25 -0500
committerOlof Johansson <olof@lixom.net>2014-11-04 23:37:25 -0500
commit83b3d538db83fe37e24b46befa699a4ae8c496f2 (patch)
tree71141d9e170e9f489db186c640ef2a3abf7f1c18 /drivers/gpu/drm/radeon/evergreen.c
parent4257412db57900e43716d0b7ddd4f4a51e6ed2f4 (diff)
parent89fbec5b97fbcf08db3a9cd93a340f21f95d38b8 (diff)
Merge tag 'imx-fixes-3.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
Merge "ARM: imx: fixes for 3.18, 2nd round" from Shawn Guo: "This is the second round of i.MX fixes for 3.18. The clk-vf610 fix is relatively big, because it needs some adaption to the change made by offending commit dc4805c2e78b (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver). And it should have been sent to you for earlier -rc inclusion, but unfortunately it got delayed for some time because Stefan wasn't aware of my email address change." The i.MX fixes for 3.18, 2nd round: - Fix a regression on Vybrid platform which is caused by commit dc4805c2e78b (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver), and results in a missing configuration on PLL clocks. - Fix a regression with i.MX defconfig files where CONFIG_SPI option gets lost accidentally. * tag 'imx-fixes-3.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (460 commits) ARM: imx: Fix the removal of CONFIG_SPI option ARM: imx: clk-vf610: define PLL's clock tree + Linux 3.18-rc3 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index a31f1ca40c6a..f37d39d2bbbc 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3005,7 +3005,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
3005 u32 vgt_cache_invalidation; 3005 u32 vgt_cache_invalidation;
3006 u32 hdp_host_path_cntl, tmp; 3006 u32 hdp_host_path_cntl, tmp;
3007 u32 disabled_rb_mask; 3007 u32 disabled_rb_mask;
3008 int i, j, num_shader_engines, ps_thread_count; 3008 int i, j, ps_thread_count;
3009 3009
3010 switch (rdev->family) { 3010 switch (rdev->family) {
3011 case CHIP_CYPRESS: 3011 case CHIP_CYPRESS:
@@ -3303,8 +3303,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
3303 rdev->config.evergreen.tile_config |= 3303 rdev->config.evergreen.tile_config |=
3304 ((gb_addr_config & 0x30000000) >> 28) << 12; 3304 ((gb_addr_config & 0x30000000) >> 28) << 12;
3305 3305
3306 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
3307
3308 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { 3306 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
3309 u32 efuse_straps_4; 3307 u32 efuse_straps_4;
3310 u32 efuse_straps_3; 3308 u32 efuse_straps_3;