diff options
author | Dave Airlie <airlied@redhat.com> | 2014-02-26 23:39:30 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2014-02-26 23:39:30 -0500 |
commit | 4d538b79197901fecc42e746d515d07fd1089b62 (patch) | |
tree | 0551acabf260fcd7c0189a4e06bb608e31d1206e /drivers/gpu/drm/radeon/evergreen.c | |
parent | c48cdd23ea5006c377b670bc3056fa7b63f92574 (diff) | |
parent | 82dc62a31ce3ed7b4eeea9c65a3b69e81e2ea688 (diff) |
Merge branch 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next
So this is the initial pull request for radeon drm-next 3.15. Highlights:
- VCE bringup including DPM support
- Few cleanups for the ring handling code
* 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux:
drm/radeon: cleanup false positive lockup handling
drm/radeon: drop radeon_ring_force_activity
drm/radeon: drop drivers copy of the rptr
drm/radeon/cik: enable/disable vce cg when encoding v2
drm/radeon: add support for vce 2.0 clock gating
drm/radeon/dpm: properly enable/disable vce when vce pg is enabled
drm/radeon/dpm: enable dynamic vce state switching v2
drm/radeon: add vce dpm support for KV/KB
drm/radeon: enable vce dpm on CI
drm/radeon: add vce dpm support for CI
drm/radeon: fill in set_vce_clocks for CIK asics
drm/radeon/dpm: fetch vce states from the vbios
drm/radeon/dpm: fill in some initial vce infrastructure
drm/radeon/dpm: move platform caps fetching to a separate function
drm/radeon: add callback for setting vce clocks
drm/radeon: add VCE version parsing and checking
drm/radeon: add VCE ring query
drm/radeon: initial VCE support v4
drm/radeon: fix CP semaphores on CIK
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 5623e7542d99..b1f1253e2ced 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -2990,8 +2990,6 @@ static int evergreen_cp_resume(struct radeon_device *rdev) | |||
2990 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); | 2990 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
2991 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | 2991 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
2992 | 2992 | ||
2993 | ring->rptr = RREG32(CP_RB_RPTR); | ||
2994 | |||
2995 | evergreen_cp_start(rdev); | 2993 | evergreen_cp_start(rdev); |
2996 | ring->ready = true; | 2994 | ring->ready = true; |
2997 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); | 2995 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
@@ -3952,11 +3950,9 @@ bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin | |||
3952 | if (!(reset_mask & (RADEON_RESET_GFX | | 3950 | if (!(reset_mask & (RADEON_RESET_GFX | |
3953 | RADEON_RESET_COMPUTE | | 3951 | RADEON_RESET_COMPUTE | |
3954 | RADEON_RESET_CP))) { | 3952 | RADEON_RESET_CP))) { |
3955 | radeon_ring_lockup_update(ring); | 3953 | radeon_ring_lockup_update(rdev, ring); |
3956 | return false; | 3954 | return false; |
3957 | } | 3955 | } |
3958 | /* force CP activities */ | ||
3959 | radeon_ring_force_activity(rdev, ring); | ||
3960 | return radeon_ring_test_lockup(rdev, ring); | 3956 | return radeon_ring_test_lockup(rdev, ring); |
3961 | } | 3957 | } |
3962 | 3958 | ||