diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2013-04-09 12:41:24 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-25 17:50:24 -0400 |
commit | 8cc1a5328b7406063812e3341e8f02718b54e3bc (patch) | |
tree | a84c7dd16390467b0af69afa4dbb00a1edaeeee8 /drivers/gpu/drm/radeon/cikd.h | |
parent | efad86db4ed09cb144bedf9fc69ae6233713f544 (diff) |
drm/radeon: add gpu init support for CIK (v9)
v2: tiling fixes
v3: more tiling fixes
v4: more tiling fixes
v5: additional register init
v6: rebase
v7: fix gb_addr_config for KV/KB
v8: drop wip KV bits for now, add missing config reg
v9: fix cu count on Bonaire
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cikd.h')
-rw-r--r-- | drivers/gpu/drm/radeon/cikd.h | 253 |
1 files changed, 253 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h new file mode 100644 index 000000000000..e51fb41a859a --- /dev/null +++ b/drivers/gpu/drm/radeon/cikd.h | |||
@@ -0,0 +1,253 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Advanced Micro Devices, Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Alex Deucher | ||
23 | */ | ||
24 | #ifndef CIK_H | ||
25 | #define CIK_H | ||
26 | |||
27 | #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 | ||
28 | |||
29 | #define CIK_RB_BITMAP_WIDTH_PER_SH 2 | ||
30 | |||
31 | #define DMIF_ADDR_CALC 0xC00 | ||
32 | |||
33 | #define MC_SHARED_CHMAP 0x2004 | ||
34 | #define NOOFCHAN_SHIFT 12 | ||
35 | #define NOOFCHAN_MASK 0x0000f000 | ||
36 | #define MC_SHARED_CHREMAP 0x2008 | ||
37 | |||
38 | #define MC_ARB_RAMCFG 0x2760 | ||
39 | #define NOOFBANK_SHIFT 0 | ||
40 | #define NOOFBANK_MASK 0x00000003 | ||
41 | #define NOOFRANK_SHIFT 2 | ||
42 | #define NOOFRANK_MASK 0x00000004 | ||
43 | #define NOOFROWS_SHIFT 3 | ||
44 | #define NOOFROWS_MASK 0x00000038 | ||
45 | #define NOOFCOLS_SHIFT 6 | ||
46 | #define NOOFCOLS_MASK 0x000000C0 | ||
47 | #define CHANSIZE_SHIFT 8 | ||
48 | #define CHANSIZE_MASK 0x00000100 | ||
49 | #define NOOFGROUPS_SHIFT 12 | ||
50 | #define NOOFGROUPS_MASK 0x00001000 | ||
51 | |||
52 | #define HDP_HOST_PATH_CNTL 0x2C00 | ||
53 | #define HDP_NONSURFACE_BASE 0x2C04 | ||
54 | #define HDP_NONSURFACE_INFO 0x2C08 | ||
55 | #define HDP_NONSURFACE_SIZE 0x2C0C | ||
56 | |||
57 | #define HDP_ADDR_CONFIG 0x2F48 | ||
58 | #define HDP_MISC_CNTL 0x2F4C | ||
59 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) | ||
60 | |||
61 | #define BIF_FB_EN 0x5490 | ||
62 | #define FB_READ_EN (1 << 0) | ||
63 | #define FB_WRITE_EN (1 << 1) | ||
64 | |||
65 | #define GRBM_CNTL 0x8000 | ||
66 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | ||
67 | |||
68 | #define CP_MEQ_THRESHOLDS 0x8764 | ||
69 | #define MEQ1_START(x) ((x) << 0) | ||
70 | #define MEQ2_START(x) ((x) << 8) | ||
71 | |||
72 | #define VGT_VTX_VECT_EJECT_REG 0x88B0 | ||
73 | |||
74 | #define VGT_CACHE_INVALIDATION 0x88C4 | ||
75 | #define CACHE_INVALIDATION(x) ((x) << 0) | ||
76 | #define VC_ONLY 0 | ||
77 | #define TC_ONLY 1 | ||
78 | #define VC_AND_TC 2 | ||
79 | #define AUTO_INVLD_EN(x) ((x) << 6) | ||
80 | #define NO_AUTO 0 | ||
81 | #define ES_AUTO 1 | ||
82 | #define GS_AUTO 2 | ||
83 | #define ES_AND_GS_AUTO 3 | ||
84 | |||
85 | #define VGT_GS_VERTEX_REUSE 0x88D4 | ||
86 | |||
87 | #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc | ||
88 | #define INACTIVE_CUS_MASK 0xFFFF0000 | ||
89 | #define INACTIVE_CUS_SHIFT 16 | ||
90 | #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 | ||
91 | |||
92 | #define PA_CL_ENHANCE 0x8A14 | ||
93 | #define CLIP_VTX_REORDER_ENA (1 << 0) | ||
94 | #define NUM_CLIP_SEQ(x) ((x) << 1) | ||
95 | |||
96 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 | ||
97 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) | ||
98 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) | ||
99 | |||
100 | #define PA_SC_FIFO_SIZE 0x8BCC | ||
101 | #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) | ||
102 | #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) | ||
103 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) | ||
104 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) | ||
105 | |||
106 | #define PA_SC_ENHANCE 0x8BF0 | ||
107 | #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) | ||
108 | #define DISABLE_PA_SC_GUIDANCE (1 << 13) | ||
109 | |||
110 | #define SQ_CONFIG 0x8C00 | ||
111 | |||
112 | #define SX_DEBUG_1 0x9060 | ||
113 | |||
114 | #define SPI_CONFIG_CNTL 0x9100 | ||
115 | |||
116 | #define SPI_CONFIG_CNTL_1 0x913C | ||
117 | #define VTX_DONE_DELAY(x) ((x) << 0) | ||
118 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | ||
119 | |||
120 | #define TA_CNTL_AUX 0x9508 | ||
121 | |||
122 | #define DB_DEBUG 0x9830 | ||
123 | #define DB_DEBUG2 0x9834 | ||
124 | #define DB_DEBUG3 0x9838 | ||
125 | |||
126 | #define CC_RB_BACKEND_DISABLE 0x98F4 | ||
127 | #define BACKEND_DISABLE(x) ((x) << 16) | ||
128 | #define GB_ADDR_CONFIG 0x98F8 | ||
129 | #define NUM_PIPES(x) ((x) << 0) | ||
130 | #define NUM_PIPES_MASK 0x00000007 | ||
131 | #define NUM_PIPES_SHIFT 0 | ||
132 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) | ||
133 | #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 | ||
134 | #define PIPE_INTERLEAVE_SIZE_SHIFT 4 | ||
135 | #define NUM_SHADER_ENGINES(x) ((x) << 12) | ||
136 | #define NUM_SHADER_ENGINES_MASK 0x00003000 | ||
137 | #define NUM_SHADER_ENGINES_SHIFT 12 | ||
138 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) | ||
139 | #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 | ||
140 | #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 | ||
141 | #define ROW_SIZE(x) ((x) << 28) | ||
142 | #define ROW_SIZE_MASK 0x30000000 | ||
143 | #define ROW_SIZE_SHIFT 28 | ||
144 | |||
145 | #define GB_TILE_MODE0 0x9910 | ||
146 | # define ARRAY_MODE(x) ((x) << 2) | ||
147 | # define ARRAY_LINEAR_GENERAL 0 | ||
148 | # define ARRAY_LINEAR_ALIGNED 1 | ||
149 | # define ARRAY_1D_TILED_THIN1 2 | ||
150 | # define ARRAY_2D_TILED_THIN1 4 | ||
151 | # define ARRAY_PRT_TILED_THIN1 5 | ||
152 | # define ARRAY_PRT_2D_TILED_THIN1 6 | ||
153 | # define PIPE_CONFIG(x) ((x) << 6) | ||
154 | # define ADDR_SURF_P2 0 | ||
155 | # define ADDR_SURF_P4_8x16 4 | ||
156 | # define ADDR_SURF_P4_16x16 5 | ||
157 | # define ADDR_SURF_P4_16x32 6 | ||
158 | # define ADDR_SURF_P4_32x32 7 | ||
159 | # define ADDR_SURF_P8_16x16_8x16 8 | ||
160 | # define ADDR_SURF_P8_16x32_8x16 9 | ||
161 | # define ADDR_SURF_P8_32x32_8x16 10 | ||
162 | # define ADDR_SURF_P8_16x32_16x16 11 | ||
163 | # define ADDR_SURF_P8_32x32_16x16 12 | ||
164 | # define ADDR_SURF_P8_32x32_16x32 13 | ||
165 | # define ADDR_SURF_P8_32x64_32x32 14 | ||
166 | # define TILE_SPLIT(x) ((x) << 11) | ||
167 | # define ADDR_SURF_TILE_SPLIT_64B 0 | ||
168 | # define ADDR_SURF_TILE_SPLIT_128B 1 | ||
169 | # define ADDR_SURF_TILE_SPLIT_256B 2 | ||
170 | # define ADDR_SURF_TILE_SPLIT_512B 3 | ||
171 | # define ADDR_SURF_TILE_SPLIT_1KB 4 | ||
172 | # define ADDR_SURF_TILE_SPLIT_2KB 5 | ||
173 | # define ADDR_SURF_TILE_SPLIT_4KB 6 | ||
174 | # define MICRO_TILE_MODE_NEW(x) ((x) << 22) | ||
175 | # define ADDR_SURF_DISPLAY_MICRO_TILING 0 | ||
176 | # define ADDR_SURF_THIN_MICRO_TILING 1 | ||
177 | # define ADDR_SURF_DEPTH_MICRO_TILING 2 | ||
178 | # define ADDR_SURF_ROTATED_MICRO_TILING 3 | ||
179 | # define SAMPLE_SPLIT(x) ((x) << 25) | ||
180 | # define ADDR_SURF_SAMPLE_SPLIT_1 0 | ||
181 | # define ADDR_SURF_SAMPLE_SPLIT_2 1 | ||
182 | # define ADDR_SURF_SAMPLE_SPLIT_4 2 | ||
183 | # define ADDR_SURF_SAMPLE_SPLIT_8 3 | ||
184 | |||
185 | #define GB_MACROTILE_MODE0 0x9990 | ||
186 | # define BANK_WIDTH(x) ((x) << 0) | ||
187 | # define ADDR_SURF_BANK_WIDTH_1 0 | ||
188 | # define ADDR_SURF_BANK_WIDTH_2 1 | ||
189 | # define ADDR_SURF_BANK_WIDTH_4 2 | ||
190 | # define ADDR_SURF_BANK_WIDTH_8 3 | ||
191 | # define BANK_HEIGHT(x) ((x) << 2) | ||
192 | # define ADDR_SURF_BANK_HEIGHT_1 0 | ||
193 | # define ADDR_SURF_BANK_HEIGHT_2 1 | ||
194 | # define ADDR_SURF_BANK_HEIGHT_4 2 | ||
195 | # define ADDR_SURF_BANK_HEIGHT_8 3 | ||
196 | # define MACRO_TILE_ASPECT(x) ((x) << 4) | ||
197 | # define ADDR_SURF_MACRO_ASPECT_1 0 | ||
198 | # define ADDR_SURF_MACRO_ASPECT_2 1 | ||
199 | # define ADDR_SURF_MACRO_ASPECT_4 2 | ||
200 | # define ADDR_SURF_MACRO_ASPECT_8 3 | ||
201 | # define NUM_BANKS(x) ((x) << 6) | ||
202 | # define ADDR_SURF_2_BANK 0 | ||
203 | # define ADDR_SURF_4_BANK 1 | ||
204 | # define ADDR_SURF_8_BANK 2 | ||
205 | # define ADDR_SURF_16_BANK 3 | ||
206 | |||
207 | #define CB_HW_CONTROL 0x9A10 | ||
208 | |||
209 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C | ||
210 | #define BACKEND_DISABLE_MASK 0x00FF0000 | ||
211 | #define BACKEND_DISABLE_SHIFT 16 | ||
212 | |||
213 | #define TCP_CHAN_STEER_LO 0xac0c | ||
214 | #define TCP_CHAN_STEER_HI 0xac10 | ||
215 | |||
216 | #define PA_SC_RASTER_CONFIG 0x28350 | ||
217 | # define RASTER_CONFIG_RB_MAP_0 0 | ||
218 | # define RASTER_CONFIG_RB_MAP_1 1 | ||
219 | # define RASTER_CONFIG_RB_MAP_2 2 | ||
220 | # define RASTER_CONFIG_RB_MAP_3 3 | ||
221 | |||
222 | #define GRBM_GFX_INDEX 0x30800 | ||
223 | #define INSTANCE_INDEX(x) ((x) << 0) | ||
224 | #define SH_INDEX(x) ((x) << 8) | ||
225 | #define SE_INDEX(x) ((x) << 16) | ||
226 | #define SH_BROADCAST_WRITES (1 << 29) | ||
227 | #define INSTANCE_BROADCAST_WRITES (1 << 30) | ||
228 | #define SE_BROADCAST_WRITES (1 << 31) | ||
229 | |||
230 | #define VGT_ESGS_RING_SIZE 0x30900 | ||
231 | #define VGT_GSVS_RING_SIZE 0x30904 | ||
232 | #define VGT_PRIMITIVE_TYPE 0x30908 | ||
233 | #define VGT_INDEX_TYPE 0x3090C | ||
234 | |||
235 | #define VGT_NUM_INDICES 0x30930 | ||
236 | #define VGT_NUM_INSTANCES 0x30934 | ||
237 | #define VGT_TF_RING_SIZE 0x30938 | ||
238 | #define VGT_HS_OFFCHIP_PARAM 0x3093C | ||
239 | #define VGT_TF_MEMORY_BASE 0x30940 | ||
240 | |||
241 | #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 | ||
242 | #define PA_SC_LINE_STIPPLE_STATE 0x30a04 | ||
243 | |||
244 | #define SQC_CACHES 0x30d20 | ||
245 | |||
246 | #define CP_PERFMON_CNTL 0x36020 | ||
247 | |||
248 | #define CGTS_TCC_DISABLE 0x3c00c | ||
249 | #define CGTS_USER_TCC_DISABLE 0x3c010 | ||
250 | #define TCC_DISABLE_MASK 0xFFFF0000 | ||
251 | #define TCC_DISABLE_SHIFT 16 | ||
252 | |||
253 | #endif | ||