diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2013-08-06 11:29:39 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2013-08-30 16:30:04 -0400 |
commit | 8a7cd27679d0451c7cf072af70acce51d15c446d (patch) | |
tree | c72d561090c1b716bf67e46fc28d7235d501b5a7 /drivers/gpu/drm/radeon/cikd.h | |
parent | 8c68e3938863460b6c224a3871d5d1ac8bb4b09f (diff) |
drm/radeon/cik: add support for pcie gen1/2/3 switching
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cikd.h')
-rw-r--r-- | drivers/gpu/drm/radeon/cikd.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 7e9275eaef80..a1f376e6dd31 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h | |||
@@ -35,6 +35,63 @@ | |||
35 | #define CG_CLKPIN_CNTL 0xC05001A0 | 35 | #define CG_CLKPIN_CNTL 0xC05001A0 |
36 | # define XTALIN_DIVIDE (1 << 1) | 36 | # define XTALIN_DIVIDE (1 << 1) |
37 | 37 | ||
38 | /* PCIE registers idx/data 0x38/0x3c */ | ||
39 | #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ | ||
40 | # define LC_REVERSE_RCVR (1 << 0) | ||
41 | # define LC_REVERSE_XMIT (1 << 1) | ||
42 | # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) | ||
43 | # define LC_OPERATING_LINK_WIDTH_SHIFT 2 | ||
44 | # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) | ||
45 | # define LC_DETECTED_LINK_WIDTH_SHIFT 5 | ||
46 | |||
47 | #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ | ||
48 | # define LC_LINK_WIDTH_SHIFT 0 | ||
49 | # define LC_LINK_WIDTH_MASK 0x7 | ||
50 | # define LC_LINK_WIDTH_X0 0 | ||
51 | # define LC_LINK_WIDTH_X1 1 | ||
52 | # define LC_LINK_WIDTH_X2 2 | ||
53 | # define LC_LINK_WIDTH_X4 3 | ||
54 | # define LC_LINK_WIDTH_X8 4 | ||
55 | # define LC_LINK_WIDTH_X16 6 | ||
56 | # define LC_LINK_WIDTH_RD_SHIFT 4 | ||
57 | # define LC_LINK_WIDTH_RD_MASK 0x70 | ||
58 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) | ||
59 | # define LC_RECONFIG_NOW (1 << 8) | ||
60 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) | ||
61 | # define LC_RENEGOTIATE_EN (1 << 10) | ||
62 | # define LC_SHORT_RECONFIG_EN (1 << 11) | ||
63 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) | ||
64 | # define LC_UPCONFIGURE_DIS (1 << 13) | ||
65 | # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) | ||
66 | # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) | ||
67 | # define LC_DYN_LANES_PWR_STATE_SHIFT 21 | ||
68 | |||
69 | #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ | ||
70 | # define LC_GEN2_EN_STRAP (1 << 0) | ||
71 | # define LC_GEN3_EN_STRAP (1 << 1) | ||
72 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) | ||
73 | # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) | ||
74 | # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 | ||
75 | # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) | ||
76 | # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) | ||
77 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) | ||
78 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) | ||
79 | # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) | ||
80 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) | ||
81 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 | ||
82 | # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ | ||
83 | # define LC_CURRENT_DATA_RATE_SHIFT 13 | ||
84 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) | ||
85 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) | ||
86 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) | ||
87 | # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) | ||
88 | # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) | ||
89 | |||
90 | #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ | ||
91 | # define LC_REDO_EQ (1 << 5) | ||
92 | # define LC_SET_QUIESCE (1 << 13) | ||
93 | |||
94 | /* direct registers */ | ||
38 | #define PCIE_INDEX 0x38 | 95 | #define PCIE_INDEX 0x38 |
39 | #define PCIE_DATA 0x3C | 96 | #define PCIE_DATA 0x3C |
40 | 97 | ||