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authorAlex Deucher <alexander.deucher@amd.com>2014-10-13 13:20:02 -0400
committerAlex Deucher <alexander.deucher@amd.com>2014-10-16 18:34:07 -0400
commitadfed2b0587289013f8143c54913ddfd44ac1fd3 (patch)
tree738a650b2b3c88d3a8c5b25315cafa42a1874720 /drivers/gpu/drm/radeon/cik_sdma.c
parent4910403836ded89803fab201d4b5caaa85de3a89 (diff)
drm/radeon: use gart memory for DMA ring tests
Avoids HDP cache flush issues when using vram which can cause ring test failures on certain boards. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Alexander Fyodorov <halcy@yandex.ru> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/cik_sdma.c')
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c21
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index c473c9125295..7deb2ef4da32 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -618,16 +618,19 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
618{ 618{
619 unsigned i; 619 unsigned i;
620 int r; 620 int r;
621 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 621 unsigned index;
622 u32 tmp; 622 u32 tmp;
623 u64 gpu_addr;
623 624
624 if (!ptr) { 625 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
625 DRM_ERROR("invalid vram scratch pointer\n"); 626 index = R600_WB_DMA_RING_TEST_OFFSET;
626 return -EINVAL; 627 else
627 } 628 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
629
630 gpu_addr = rdev->wb.gpu_addr + index;
628 631
629 tmp = 0xCAFEDEAD; 632 tmp = 0xCAFEDEAD;
630 writel(tmp, ptr); 633 rdev->wb.wb[index/4] = cpu_to_le32(tmp);
631 634
632 r = radeon_ring_lock(rdev, ring, 5); 635 r = radeon_ring_lock(rdev, ring, 5);
633 if (r) { 636 if (r) {
@@ -635,14 +638,14 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
635 return r; 638 return r;
636 } 639 }
637 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 640 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
638 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 641 radeon_ring_write(ring, lower_32_bits(gpu_addr));
639 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr)); 642 radeon_ring_write(ring, upper_32_bits(gpu_addr));
640 radeon_ring_write(ring, 1); /* number of DWs to follow */ 643 radeon_ring_write(ring, 1); /* number of DWs to follow */
641 radeon_ring_write(ring, 0xDEADBEEF); 644 radeon_ring_write(ring, 0xDEADBEEF);
642 radeon_ring_unlock_commit(rdev, ring, false); 645 radeon_ring_unlock_commit(rdev, ring, false);
643 646
644 for (i = 0; i < rdev->usec_timeout; i++) { 647 for (i = 0; i < rdev->usec_timeout; i++) {
645 tmp = readl(ptr); 648 tmp = le32_to_cpu(rdev->wb.wb[index/4]);
646 if (tmp == 0xDEADBEEF) 649 if (tmp == 0xDEADBEEF)
647 break; 650 break;
648 DRM_UDELAY(1); 651 DRM_UDELAY(1);