diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2013-01-29 10:44:22 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-26 16:11:51 -0400 |
commit | b556b12e829c504bd3d1044e28ffbae2385b6fdc (patch) | |
tree | e562ccea91da3954884364b3ff3bb0a7932bb0eb /drivers/gpu/drm/radeon/cik.c | |
parent | 87167bb16dfdd76b836ed3c19024c4a2d985f993 (diff) |
drm/radeon/cik: add srbm_select function
Allows us to select instanced registers based on:
- ME (micro engine
- Pipe
- Queue
- VMID
Switch MC setup to use this new function.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
-rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 3e32b145341f..a61c373c2bc3 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -163,6 +163,29 @@ static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] = | |||
163 | {0x0000009f, 0x00b48000} | 163 | {0x0000009f, 0x00b48000} |
164 | }; | 164 | }; |
165 | 165 | ||
166 | /** | ||
167 | * cik_srbm_select - select specific register instances | ||
168 | * | ||
169 | * @rdev: radeon_device pointer | ||
170 | * @me: selected ME (micro engine) | ||
171 | * @pipe: pipe | ||
172 | * @queue: queue | ||
173 | * @vmid: VMID | ||
174 | * | ||
175 | * Switches the currently active registers instances. Some | ||
176 | * registers are instanced per VMID, others are instanced per | ||
177 | * me/pipe/queue combination. | ||
178 | */ | ||
179 | static void cik_srbm_select(struct radeon_device *rdev, | ||
180 | u32 me, u32 pipe, u32 queue, u32 vmid) | ||
181 | { | ||
182 | u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) | | ||
183 | MEID(me & 0x3) | | ||
184 | VMID(vmid & 0xf) | | ||
185 | QUEUEID(queue & 0x7)); | ||
186 | WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); | ||
187 | } | ||
188 | |||
166 | /* ucode loading */ | 189 | /* ucode loading */ |
167 | /** | 190 | /** |
168 | * ci_mc_load_microcode - load MC ucode into the hw | 191 | * ci_mc_load_microcode - load MC ucode into the hw |
@@ -3351,7 +3374,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) | |||
3351 | /* XXX SH_MEM regs */ | 3374 | /* XXX SH_MEM regs */ |
3352 | /* where to put LDS, scratch, GPUVM in FSA64 space */ | 3375 | /* where to put LDS, scratch, GPUVM in FSA64 space */ |
3353 | for (i = 0; i < 16; i++) { | 3376 | for (i = 0; i < 16; i++) { |
3354 | WREG32(SRBM_GFX_CNTL, VMID(i)); | 3377 | cik_srbm_select(rdev, 0, 0, 0, i); |
3355 | /* CP and shaders */ | 3378 | /* CP and shaders */ |
3356 | WREG32(SH_MEM_CONFIG, 0); | 3379 | WREG32(SH_MEM_CONFIG, 0); |
3357 | WREG32(SH_MEM_APE1_BASE, 1); | 3380 | WREG32(SH_MEM_APE1_BASE, 1); |
@@ -3364,7 +3387,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) | |||
3364 | WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); | 3387 | WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); |
3365 | /* XXX SDMA RLC - todo */ | 3388 | /* XXX SDMA RLC - todo */ |
3366 | } | 3389 | } |
3367 | WREG32(SRBM_GFX_CNTL, 0); | 3390 | cik_srbm_select(rdev, 0, 0, 0, 0); |
3368 | 3391 | ||
3369 | cik_pcie_gart_tlb_flush(rdev); | 3392 | cik_pcie_gart_tlb_flush(rdev); |
3370 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", | 3393 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |