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authorAlex Deucher <alexander.deucher@amd.com>2013-06-26 00:15:24 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 19:15:44 -0400
commit6596afd48af4d07c8b454849b2fe7e628974f3ef (patch)
tree4a6a081ef0f3b6cc96afc36c65ff502129072bd1 /drivers/gpu/drm/radeon/btc_dpm.c
parentdc50ba7f9a6d9a920409892c7f30bce266067345 (diff)
drm/radeon/kms: add dpm support for btc (v3)
This adds dpm support for btc asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) Set radeon.dpm=1 to enable. v2: reduce stack usage v3: attempt to fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/btc_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/btc_dpm.c2188
1 files changed, 2188 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
new file mode 100644
index 000000000000..221d4c6b95c5
--- /dev/null
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -0,0 +1,2188 @@
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include "drmP.h"
26#include "radeon.h"
27#include "btcd.h"
28#include "r600_dpm.h"
29#include "cypress_dpm.h"
30#include "btc_dpm.h"
31#include "atom.h"
32
33#define MC_CG_ARB_FREQ_F0 0x0a
34#define MC_CG_ARB_FREQ_F1 0x0b
35#define MC_CG_ARB_FREQ_F2 0x0c
36#define MC_CG_ARB_FREQ_F3 0x0d
37
38#define MC_CG_SEQ_DRAMCONF_S0 0x05
39#define MC_CG_SEQ_DRAMCONF_S1 0x06
40#define MC_CG_SEQ_YCLK_SUSPEND 0x04
41#define MC_CG_SEQ_YCLK_RESUME 0x0a
42
43#define SMC_RAM_END 0x8000
44
45#ifndef BTC_MGCG_SEQUENCE
46#define BTC_MGCG_SEQUENCE 300
47
48struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
49struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
50struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
51
52
53//********* BARTS **************//
54static const u32 barts_cgcg_cgls_default[] =
55{
56 /* Register, Value, Mask bits */
57 0x000008f8, 0x00000010, 0xffffffff,
58 0x000008fc, 0x00000000, 0xffffffff,
59 0x000008f8, 0x00000011, 0xffffffff,
60 0x000008fc, 0x00000000, 0xffffffff,
61 0x000008f8, 0x00000012, 0xffffffff,
62 0x000008fc, 0x00000000, 0xffffffff,
63 0x000008f8, 0x00000013, 0xffffffff,
64 0x000008fc, 0x00000000, 0xffffffff,
65 0x000008f8, 0x00000014, 0xffffffff,
66 0x000008fc, 0x00000000, 0xffffffff,
67 0x000008f8, 0x00000015, 0xffffffff,
68 0x000008fc, 0x00000000, 0xffffffff,
69 0x000008f8, 0x00000016, 0xffffffff,
70 0x000008fc, 0x00000000, 0xffffffff,
71 0x000008f8, 0x00000017, 0xffffffff,
72 0x000008fc, 0x00000000, 0xffffffff,
73 0x000008f8, 0x00000018, 0xffffffff,
74 0x000008fc, 0x00000000, 0xffffffff,
75 0x000008f8, 0x00000019, 0xffffffff,
76 0x000008fc, 0x00000000, 0xffffffff,
77 0x000008f8, 0x0000001a, 0xffffffff,
78 0x000008fc, 0x00000000, 0xffffffff,
79 0x000008f8, 0x0000001b, 0xffffffff,
80 0x000008fc, 0x00000000, 0xffffffff,
81 0x000008f8, 0x00000020, 0xffffffff,
82 0x000008fc, 0x00000000, 0xffffffff,
83 0x000008f8, 0x00000021, 0xffffffff,
84 0x000008fc, 0x00000000, 0xffffffff,
85 0x000008f8, 0x00000022, 0xffffffff,
86 0x000008fc, 0x00000000, 0xffffffff,
87 0x000008f8, 0x00000023, 0xffffffff,
88 0x000008fc, 0x00000000, 0xffffffff,
89 0x000008f8, 0x00000024, 0xffffffff,
90 0x000008fc, 0x00000000, 0xffffffff,
91 0x000008f8, 0x00000025, 0xffffffff,
92 0x000008fc, 0x00000000, 0xffffffff,
93 0x000008f8, 0x00000026, 0xffffffff,
94 0x000008fc, 0x00000000, 0xffffffff,
95 0x000008f8, 0x00000027, 0xffffffff,
96 0x000008fc, 0x00000000, 0xffffffff,
97 0x000008f8, 0x00000028, 0xffffffff,
98 0x000008fc, 0x00000000, 0xffffffff,
99 0x000008f8, 0x00000029, 0xffffffff,
100 0x000008fc, 0x00000000, 0xffffffff,
101 0x000008f8, 0x0000002a, 0xffffffff,
102 0x000008fc, 0x00000000, 0xffffffff,
103 0x000008f8, 0x0000002b, 0xffffffff,
104 0x000008fc, 0x00000000, 0xffffffff
105};
106#define BARTS_CGCG_CGLS_DEFAULT_LENGTH sizeof(barts_cgcg_cgls_default) / (3 * sizeof(u32))
107
108static const u32 barts_cgcg_cgls_disable[] =
109{
110 0x000008f8, 0x00000010, 0xffffffff,
111 0x000008fc, 0xffffffff, 0xffffffff,
112 0x000008f8, 0x00000011, 0xffffffff,
113 0x000008fc, 0xffffffff, 0xffffffff,
114 0x000008f8, 0x00000012, 0xffffffff,
115 0x000008fc, 0xffffffff, 0xffffffff,
116 0x000008f8, 0x00000013, 0xffffffff,
117 0x000008fc, 0xffffffff, 0xffffffff,
118 0x000008f8, 0x00000014, 0xffffffff,
119 0x000008fc, 0xffffffff, 0xffffffff,
120 0x000008f8, 0x00000015, 0xffffffff,
121 0x000008fc, 0xffffffff, 0xffffffff,
122 0x000008f8, 0x00000016, 0xffffffff,
123 0x000008fc, 0xffffffff, 0xffffffff,
124 0x000008f8, 0x00000017, 0xffffffff,
125 0x000008fc, 0xffffffff, 0xffffffff,
126 0x000008f8, 0x00000018, 0xffffffff,
127 0x000008fc, 0xffffffff, 0xffffffff,
128 0x000008f8, 0x00000019, 0xffffffff,
129 0x000008fc, 0xffffffff, 0xffffffff,
130 0x000008f8, 0x0000001a, 0xffffffff,
131 0x000008fc, 0xffffffff, 0xffffffff,
132 0x000008f8, 0x0000001b, 0xffffffff,
133 0x000008fc, 0xffffffff, 0xffffffff,
134 0x000008f8, 0x00000020, 0xffffffff,
135 0x000008fc, 0x00000000, 0xffffffff,
136 0x000008f8, 0x00000021, 0xffffffff,
137 0x000008fc, 0x00000000, 0xffffffff,
138 0x000008f8, 0x00000022, 0xffffffff,
139 0x000008fc, 0x00000000, 0xffffffff,
140 0x000008f8, 0x00000023, 0xffffffff,
141 0x000008fc, 0x00000000, 0xffffffff,
142 0x000008f8, 0x00000024, 0xffffffff,
143 0x000008fc, 0x00000000, 0xffffffff,
144 0x000008f8, 0x00000025, 0xffffffff,
145 0x000008fc, 0x00000000, 0xffffffff,
146 0x000008f8, 0x00000026, 0xffffffff,
147 0x000008fc, 0x00000000, 0xffffffff,
148 0x000008f8, 0x00000027, 0xffffffff,
149 0x000008fc, 0x00000000, 0xffffffff,
150 0x000008f8, 0x00000028, 0xffffffff,
151 0x000008fc, 0x00000000, 0xffffffff,
152 0x000008f8, 0x00000029, 0xffffffff,
153 0x000008fc, 0x00000000, 0xffffffff,
154 0x000008f8, 0x0000002a, 0xffffffff,
155 0x000008fc, 0x00000000, 0xffffffff,
156 0x000008f8, 0x0000002b, 0xffffffff,
157 0x000008fc, 0x00000000, 0xffffffff,
158 0x00000644, 0x000f7912, 0x001f4180,
159 0x00000644, 0x000f3812, 0x001f4180
160};
161#define BARTS_CGCG_CGLS_DISABLE_LENGTH sizeof(barts_cgcg_cgls_disable) / (3 * sizeof(u32))
162
163static const u32 barts_cgcg_cgls_enable[] =
164{
165 /* 0x0000c124, 0x84180000, 0x00180000, */
166 0x00000644, 0x000f7892, 0x001f4080,
167 0x000008f8, 0x00000010, 0xffffffff,
168 0x000008fc, 0x00000000, 0xffffffff,
169 0x000008f8, 0x00000011, 0xffffffff,
170 0x000008fc, 0x00000000, 0xffffffff,
171 0x000008f8, 0x00000012, 0xffffffff,
172 0x000008fc, 0x00000000, 0xffffffff,
173 0x000008f8, 0x00000013, 0xffffffff,
174 0x000008fc, 0x00000000, 0xffffffff,
175 0x000008f8, 0x00000014, 0xffffffff,
176 0x000008fc, 0x00000000, 0xffffffff,
177 0x000008f8, 0x00000015, 0xffffffff,
178 0x000008fc, 0x00000000, 0xffffffff,
179 0x000008f8, 0x00000016, 0xffffffff,
180 0x000008fc, 0x00000000, 0xffffffff,
181 0x000008f8, 0x00000017, 0xffffffff,
182 0x000008fc, 0x00000000, 0xffffffff,
183 0x000008f8, 0x00000018, 0xffffffff,
184 0x000008fc, 0x00000000, 0xffffffff,
185 0x000008f8, 0x00000019, 0xffffffff,
186 0x000008fc, 0x00000000, 0xffffffff,
187 0x000008f8, 0x0000001a, 0xffffffff,
188 0x000008fc, 0x00000000, 0xffffffff,
189 0x000008f8, 0x0000001b, 0xffffffff,
190 0x000008fc, 0x00000000, 0xffffffff,
191 0x000008f8, 0x00000020, 0xffffffff,
192 0x000008fc, 0xffffffff, 0xffffffff,
193 0x000008f8, 0x00000021, 0xffffffff,
194 0x000008fc, 0xffffffff, 0xffffffff,
195 0x000008f8, 0x00000022, 0xffffffff,
196 0x000008fc, 0xffffffff, 0xffffffff,
197 0x000008f8, 0x00000023, 0xffffffff,
198 0x000008fc, 0xffffffff, 0xffffffff,
199 0x000008f8, 0x00000024, 0xffffffff,
200 0x000008fc, 0xffffffff, 0xffffffff,
201 0x000008f8, 0x00000025, 0xffffffff,
202 0x000008fc, 0xffffffff, 0xffffffff,
203 0x000008f8, 0x00000026, 0xffffffff,
204 0x000008fc, 0xffffffff, 0xffffffff,
205 0x000008f8, 0x00000027, 0xffffffff,
206 0x000008fc, 0xffffffff, 0xffffffff,
207 0x000008f8, 0x00000028, 0xffffffff,
208 0x000008fc, 0xffffffff, 0xffffffff,
209 0x000008f8, 0x00000029, 0xffffffff,
210 0x000008fc, 0xffffffff, 0xffffffff,
211 0x000008f8, 0x0000002a, 0xffffffff,
212 0x000008fc, 0xffffffff, 0xffffffff,
213 0x000008f8, 0x0000002b, 0xffffffff,
214 0x000008fc, 0xffffffff, 0xffffffff
215};
216#define BARTS_CGCG_CGLS_ENABLE_LENGTH sizeof(barts_cgcg_cgls_enable) / (3 * sizeof(u32))
217
218static const u32 barts_mgcg_default[] =
219{
220 0x0000802c, 0xc0000000, 0xffffffff,
221 0x00005448, 0x00000100, 0xffffffff,
222 0x000055e4, 0x00600100, 0xffffffff,
223 0x0000160c, 0x00000100, 0xffffffff,
224 0x0000c164, 0x00000100, 0xffffffff,
225 0x00008a18, 0x00000100, 0xffffffff,
226 0x0000897c, 0x06000100, 0xffffffff,
227 0x00008b28, 0x00000100, 0xffffffff,
228 0x00009144, 0x00000100, 0xffffffff,
229 0x00009a60, 0x00000100, 0xffffffff,
230 0x00009868, 0x00000100, 0xffffffff,
231 0x00008d58, 0x00000100, 0xffffffff,
232 0x00009510, 0x00000100, 0xffffffff,
233 0x0000949c, 0x00000100, 0xffffffff,
234 0x00009654, 0x00000100, 0xffffffff,
235 0x00009030, 0x00000100, 0xffffffff,
236 0x00009034, 0x00000100, 0xffffffff,
237 0x00009038, 0x00000100, 0xffffffff,
238 0x0000903c, 0x00000100, 0xffffffff,
239 0x00009040, 0x00000100, 0xffffffff,
240 0x0000a200, 0x00000100, 0xffffffff,
241 0x0000a204, 0x00000100, 0xffffffff,
242 0x0000a208, 0x00000100, 0xffffffff,
243 0x0000a20c, 0x00000100, 0xffffffff,
244 0x0000977c, 0x00000100, 0xffffffff,
245 0x00003f80, 0x00000100, 0xffffffff,
246 0x0000a210, 0x00000100, 0xffffffff,
247 0x0000a214, 0x00000100, 0xffffffff,
248 0x000004d8, 0x00000100, 0xffffffff,
249 0x00009784, 0x00000100, 0xffffffff,
250 0x00009698, 0x00000100, 0xffffffff,
251 0x000004d4, 0x00000200, 0xffffffff,
252 0x000004d0, 0x00000000, 0xffffffff,
253 0x000030cc, 0x00000100, 0xffffffff,
254 0x0000d0c0, 0xff000100, 0xffffffff,
255 0x0000802c, 0x40000000, 0xffffffff,
256 0x0000915c, 0x00010000, 0xffffffff,
257 0x00009160, 0x00030002, 0xffffffff,
258 0x00009164, 0x00050004, 0xffffffff,
259 0x00009168, 0x00070006, 0xffffffff,
260 0x00009178, 0x00070000, 0xffffffff,
261 0x0000917c, 0x00030002, 0xffffffff,
262 0x00009180, 0x00050004, 0xffffffff,
263 0x0000918c, 0x00010006, 0xffffffff,
264 0x00009190, 0x00090008, 0xffffffff,
265 0x00009194, 0x00070000, 0xffffffff,
266 0x00009198, 0x00030002, 0xffffffff,
267 0x0000919c, 0x00050004, 0xffffffff,
268 0x000091a8, 0x00010006, 0xffffffff,
269 0x000091ac, 0x00090008, 0xffffffff,
270 0x000091b0, 0x00070000, 0xffffffff,
271 0x000091b4, 0x00030002, 0xffffffff,
272 0x000091b8, 0x00050004, 0xffffffff,
273 0x000091c4, 0x00010006, 0xffffffff,
274 0x000091c8, 0x00090008, 0xffffffff,
275 0x000091cc, 0x00070000, 0xffffffff,
276 0x000091d0, 0x00030002, 0xffffffff,
277 0x000091d4, 0x00050004, 0xffffffff,
278 0x000091e0, 0x00010006, 0xffffffff,
279 0x000091e4, 0x00090008, 0xffffffff,
280 0x000091e8, 0x00000000, 0xffffffff,
281 0x000091ec, 0x00070000, 0xffffffff,
282 0x000091f0, 0x00030002, 0xffffffff,
283 0x000091f4, 0x00050004, 0xffffffff,
284 0x00009200, 0x00010006, 0xffffffff,
285 0x00009204, 0x00090008, 0xffffffff,
286 0x00009208, 0x00070000, 0xffffffff,
287 0x0000920c, 0x00030002, 0xffffffff,
288 0x00009210, 0x00050004, 0xffffffff,
289 0x0000921c, 0x00010006, 0xffffffff,
290 0x00009220, 0x00090008, 0xffffffff,
291 0x00009224, 0x00070000, 0xffffffff,
292 0x00009228, 0x00030002, 0xffffffff,
293 0x0000922c, 0x00050004, 0xffffffff,
294 0x00009238, 0x00010006, 0xffffffff,
295 0x0000923c, 0x00090008, 0xffffffff,
296 0x00009294, 0x00000000, 0xffffffff,
297 0x0000802c, 0x40010000, 0xffffffff,
298 0x0000915c, 0x00010000, 0xffffffff,
299 0x00009160, 0x00030002, 0xffffffff,
300 0x00009164, 0x00050004, 0xffffffff,
301 0x00009168, 0x00070006, 0xffffffff,
302 0x00009178, 0x00070000, 0xffffffff,
303 0x0000917c, 0x00030002, 0xffffffff,
304 0x00009180, 0x00050004, 0xffffffff,
305 0x0000918c, 0x00010006, 0xffffffff,
306 0x00009190, 0x00090008, 0xffffffff,
307 0x00009194, 0x00070000, 0xffffffff,
308 0x00009198, 0x00030002, 0xffffffff,
309 0x0000919c, 0x00050004, 0xffffffff,
310 0x000091a8, 0x00010006, 0xffffffff,
311 0x000091ac, 0x00090008, 0xffffffff,
312 0x000091b0, 0x00070000, 0xffffffff,
313 0x000091b4, 0x00030002, 0xffffffff,
314 0x000091b8, 0x00050004, 0xffffffff,
315 0x000091c4, 0x00010006, 0xffffffff,
316 0x000091c8, 0x00090008, 0xffffffff,
317 0x000091cc, 0x00070000, 0xffffffff,
318 0x000091d0, 0x00030002, 0xffffffff,
319 0x000091d4, 0x00050004, 0xffffffff,
320 0x000091e0, 0x00010006, 0xffffffff,
321 0x000091e4, 0x00090008, 0xffffffff,
322 0x000091e8, 0x00000000, 0xffffffff,
323 0x000091ec, 0x00070000, 0xffffffff,
324 0x000091f0, 0x00030002, 0xffffffff,
325 0x000091f4, 0x00050004, 0xffffffff,
326 0x00009200, 0x00010006, 0xffffffff,
327 0x00009204, 0x00090008, 0xffffffff,
328 0x00009208, 0x00070000, 0xffffffff,
329 0x0000920c, 0x00030002, 0xffffffff,
330 0x00009210, 0x00050004, 0xffffffff,
331 0x0000921c, 0x00010006, 0xffffffff,
332 0x00009220, 0x00090008, 0xffffffff,
333 0x00009224, 0x00070000, 0xffffffff,
334 0x00009228, 0x00030002, 0xffffffff,
335 0x0000922c, 0x00050004, 0xffffffff,
336 0x00009238, 0x00010006, 0xffffffff,
337 0x0000923c, 0x00090008, 0xffffffff,
338 0x00009294, 0x00000000, 0xffffffff,
339 0x0000802c, 0xc0000000, 0xffffffff,
340 0x000008f8, 0x00000010, 0xffffffff,
341 0x000008fc, 0x00000000, 0xffffffff,
342 0x000008f8, 0x00000011, 0xffffffff,
343 0x000008fc, 0x00000000, 0xffffffff,
344 0x000008f8, 0x00000012, 0xffffffff,
345 0x000008fc, 0x00000000, 0xffffffff,
346 0x000008f8, 0x00000013, 0xffffffff,
347 0x000008fc, 0x00000000, 0xffffffff,
348 0x000008f8, 0x00000014, 0xffffffff,
349 0x000008fc, 0x00000000, 0xffffffff,
350 0x000008f8, 0x00000015, 0xffffffff,
351 0x000008fc, 0x00000000, 0xffffffff,
352 0x000008f8, 0x00000016, 0xffffffff,
353 0x000008fc, 0x00000000, 0xffffffff,
354 0x000008f8, 0x00000017, 0xffffffff,
355 0x000008fc, 0x00000000, 0xffffffff,
356 0x000008f8, 0x00000018, 0xffffffff,
357 0x000008fc, 0x00000000, 0xffffffff,
358 0x000008f8, 0x00000019, 0xffffffff,
359 0x000008fc, 0x00000000, 0xffffffff,
360 0x000008f8, 0x0000001a, 0xffffffff,
361 0x000008fc, 0x00000000, 0xffffffff,
362 0x000008f8, 0x0000001b, 0xffffffff,
363 0x000008fc, 0x00000000, 0xffffffff
364};
365#define BARTS_MGCG_DEFAULT_LENGTH sizeof(barts_mgcg_default) / (3 * sizeof(u32))
366
367static const u32 barts_mgcg_disable[] =
368{
369 0x0000802c, 0xc0000000, 0xffffffff,
370 0x000008f8, 0x00000000, 0xffffffff,
371 0x000008fc, 0xffffffff, 0xffffffff,
372 0x000008f8, 0x00000001, 0xffffffff,
373 0x000008fc, 0xffffffff, 0xffffffff,
374 0x000008f8, 0x00000002, 0xffffffff,
375 0x000008fc, 0xffffffff, 0xffffffff,
376 0x000008f8, 0x00000003, 0xffffffff,
377 0x000008fc, 0xffffffff, 0xffffffff,
378 0x00009150, 0x00600000, 0xffffffff
379};
380#define BARTS_MGCG_DISABLE_LENGTH sizeof(barts_mgcg_disable) / (3 * sizeof(u32))
381
382static const u32 barts_mgcg_enable[] =
383{
384 0x0000802c, 0xc0000000, 0xffffffff,
385 0x000008f8, 0x00000000, 0xffffffff,
386 0x000008fc, 0x00000000, 0xffffffff,
387 0x000008f8, 0x00000001, 0xffffffff,
388 0x000008fc, 0x00000000, 0xffffffff,
389 0x000008f8, 0x00000002, 0xffffffff,
390 0x000008fc, 0x00000000, 0xffffffff,
391 0x000008f8, 0x00000003, 0xffffffff,
392 0x000008fc, 0x00000000, 0xffffffff,
393 0x00009150, 0x81944000, 0xffffffff
394};
395#define BARTS_MGCG_ENABLE_LENGTH sizeof(barts_mgcg_enable) / (3 * sizeof(u32))
396
397//********* CAICOS **************//
398static const u32 caicos_cgcg_cgls_default[] =
399{
400 0x000008f8, 0x00000010, 0xffffffff,
401 0x000008fc, 0x00000000, 0xffffffff,
402 0x000008f8, 0x00000011, 0xffffffff,
403 0x000008fc, 0x00000000, 0xffffffff,
404 0x000008f8, 0x00000012, 0xffffffff,
405 0x000008fc, 0x00000000, 0xffffffff,
406 0x000008f8, 0x00000013, 0xffffffff,
407 0x000008fc, 0x00000000, 0xffffffff,
408 0x000008f8, 0x00000014, 0xffffffff,
409 0x000008fc, 0x00000000, 0xffffffff,
410 0x000008f8, 0x00000015, 0xffffffff,
411 0x000008fc, 0x00000000, 0xffffffff,
412 0x000008f8, 0x00000016, 0xffffffff,
413 0x000008fc, 0x00000000, 0xffffffff,
414 0x000008f8, 0x00000017, 0xffffffff,
415 0x000008fc, 0x00000000, 0xffffffff,
416 0x000008f8, 0x00000018, 0xffffffff,
417 0x000008fc, 0x00000000, 0xffffffff,
418 0x000008f8, 0x00000019, 0xffffffff,
419 0x000008fc, 0x00000000, 0xffffffff,
420 0x000008f8, 0x0000001a, 0xffffffff,
421 0x000008fc, 0x00000000, 0xffffffff,
422 0x000008f8, 0x0000001b, 0xffffffff,
423 0x000008fc, 0x00000000, 0xffffffff,
424 0x000008f8, 0x00000020, 0xffffffff,
425 0x000008fc, 0x00000000, 0xffffffff,
426 0x000008f8, 0x00000021, 0xffffffff,
427 0x000008fc, 0x00000000, 0xffffffff,
428 0x000008f8, 0x00000022, 0xffffffff,
429 0x000008fc, 0x00000000, 0xffffffff,
430 0x000008f8, 0x00000023, 0xffffffff,
431 0x000008fc, 0x00000000, 0xffffffff,
432 0x000008f8, 0x00000024, 0xffffffff,
433 0x000008fc, 0x00000000, 0xffffffff,
434 0x000008f8, 0x00000025, 0xffffffff,
435 0x000008fc, 0x00000000, 0xffffffff,
436 0x000008f8, 0x00000026, 0xffffffff,
437 0x000008fc, 0x00000000, 0xffffffff,
438 0x000008f8, 0x00000027, 0xffffffff,
439 0x000008fc, 0x00000000, 0xffffffff,
440 0x000008f8, 0x00000028, 0xffffffff,
441 0x000008fc, 0x00000000, 0xffffffff,
442 0x000008f8, 0x00000029, 0xffffffff,
443 0x000008fc, 0x00000000, 0xffffffff,
444 0x000008f8, 0x0000002a, 0xffffffff,
445 0x000008fc, 0x00000000, 0xffffffff,
446 0x000008f8, 0x0000002b, 0xffffffff,
447 0x000008fc, 0x00000000, 0xffffffff
448};
449#define CAICOS_CGCG_CGLS_DEFAULT_LENGTH sizeof(caicos_cgcg_cgls_default) / (3 * sizeof(u32))
450
451static const u32 caicos_cgcg_cgls_disable[] =
452{
453 0x000008f8, 0x00000010, 0xffffffff,
454 0x000008fc, 0xffffffff, 0xffffffff,
455 0x000008f8, 0x00000011, 0xffffffff,
456 0x000008fc, 0xffffffff, 0xffffffff,
457 0x000008f8, 0x00000012, 0xffffffff,
458 0x000008fc, 0xffffffff, 0xffffffff,
459 0x000008f8, 0x00000013, 0xffffffff,
460 0x000008fc, 0xffffffff, 0xffffffff,
461 0x000008f8, 0x00000014, 0xffffffff,
462 0x000008fc, 0xffffffff, 0xffffffff,
463 0x000008f8, 0x00000015, 0xffffffff,
464 0x000008fc, 0xffffffff, 0xffffffff,
465 0x000008f8, 0x00000016, 0xffffffff,
466 0x000008fc, 0xffffffff, 0xffffffff,
467 0x000008f8, 0x00000017, 0xffffffff,
468 0x000008fc, 0xffffffff, 0xffffffff,
469 0x000008f8, 0x00000018, 0xffffffff,
470 0x000008fc, 0xffffffff, 0xffffffff,
471 0x000008f8, 0x00000019, 0xffffffff,
472 0x000008fc, 0xffffffff, 0xffffffff,
473 0x000008f8, 0x0000001a, 0xffffffff,
474 0x000008fc, 0xffffffff, 0xffffffff,
475 0x000008f8, 0x0000001b, 0xffffffff,
476 0x000008fc, 0xffffffff, 0xffffffff,
477 0x000008f8, 0x00000020, 0xffffffff,
478 0x000008fc, 0x00000000, 0xffffffff,
479 0x000008f8, 0x00000021, 0xffffffff,
480 0x000008fc, 0x00000000, 0xffffffff,
481 0x000008f8, 0x00000022, 0xffffffff,
482 0x000008fc, 0x00000000, 0xffffffff,
483 0x000008f8, 0x00000023, 0xffffffff,
484 0x000008fc, 0x00000000, 0xffffffff,
485 0x000008f8, 0x00000024, 0xffffffff,
486 0x000008fc, 0x00000000, 0xffffffff,
487 0x000008f8, 0x00000025, 0xffffffff,
488 0x000008fc, 0x00000000, 0xffffffff,
489 0x000008f8, 0x00000026, 0xffffffff,
490 0x000008fc, 0x00000000, 0xffffffff,
491 0x000008f8, 0x00000027, 0xffffffff,
492 0x000008fc, 0x00000000, 0xffffffff,
493 0x000008f8, 0x00000028, 0xffffffff,
494 0x000008fc, 0x00000000, 0xffffffff,
495 0x000008f8, 0x00000029, 0xffffffff,
496 0x000008fc, 0x00000000, 0xffffffff,
497 0x000008f8, 0x0000002a, 0xffffffff,
498 0x000008fc, 0x00000000, 0xffffffff,
499 0x000008f8, 0x0000002b, 0xffffffff,
500 0x000008fc, 0x00000000, 0xffffffff,
501 0x00000644, 0x000f7912, 0x001f4180,
502 0x00000644, 0x000f3812, 0x001f4180
503};
504#define CAICOS_CGCG_CGLS_DISABLE_LENGTH sizeof(caicos_cgcg_cgls_disable) / (3 * sizeof(u32))
505
506static const u32 caicos_cgcg_cgls_enable[] =
507{
508 /* 0x0000c124, 0x84180000, 0x00180000, */
509 0x00000644, 0x000f7892, 0x001f4080,
510 0x000008f8, 0x00000010, 0xffffffff,
511 0x000008fc, 0x00000000, 0xffffffff,
512 0x000008f8, 0x00000011, 0xffffffff,
513 0x000008fc, 0x00000000, 0xffffffff,
514 0x000008f8, 0x00000012, 0xffffffff,
515 0x000008fc, 0x00000000, 0xffffffff,
516 0x000008f8, 0x00000013, 0xffffffff,
517 0x000008fc, 0x00000000, 0xffffffff,
518 0x000008f8, 0x00000014, 0xffffffff,
519 0x000008fc, 0x00000000, 0xffffffff,
520 0x000008f8, 0x00000015, 0xffffffff,
521 0x000008fc, 0x00000000, 0xffffffff,
522 0x000008f8, 0x00000016, 0xffffffff,
523 0x000008fc, 0x00000000, 0xffffffff,
524 0x000008f8, 0x00000017, 0xffffffff,
525 0x000008fc, 0x00000000, 0xffffffff,
526 0x000008f8, 0x00000018, 0xffffffff,
527 0x000008fc, 0x00000000, 0xffffffff,
528 0x000008f8, 0x00000019, 0xffffffff,
529 0x000008fc, 0x00000000, 0xffffffff,
530 0x000008f8, 0x0000001a, 0xffffffff,
531 0x000008fc, 0x00000000, 0xffffffff,
532 0x000008f8, 0x0000001b, 0xffffffff,
533 0x000008fc, 0x00000000, 0xffffffff,
534 0x000008f8, 0x00000020, 0xffffffff,
535 0x000008fc, 0xffffffff, 0xffffffff,
536 0x000008f8, 0x00000021, 0xffffffff,
537 0x000008fc, 0xffffffff, 0xffffffff,
538 0x000008f8, 0x00000022, 0xffffffff,
539 0x000008fc, 0xffffffff, 0xffffffff,
540 0x000008f8, 0x00000023, 0xffffffff,
541 0x000008fc, 0xffffffff, 0xffffffff,
542 0x000008f8, 0x00000024, 0xffffffff,
543 0x000008fc, 0xffffffff, 0xffffffff,
544 0x000008f8, 0x00000025, 0xffffffff,
545 0x000008fc, 0xffffffff, 0xffffffff,
546 0x000008f8, 0x00000026, 0xffffffff,
547 0x000008fc, 0xffffffff, 0xffffffff,
548 0x000008f8, 0x00000027, 0xffffffff,
549 0x000008fc, 0xffffffff, 0xffffffff,
550 0x000008f8, 0x00000028, 0xffffffff,
551 0x000008fc, 0xffffffff, 0xffffffff,
552 0x000008f8, 0x00000029, 0xffffffff,
553 0x000008fc, 0xffffffff, 0xffffffff,
554 0x000008f8, 0x0000002a, 0xffffffff,
555 0x000008fc, 0xffffffff, 0xffffffff,
556 0x000008f8, 0x0000002b, 0xffffffff,
557 0x000008fc, 0xffffffff, 0xffffffff
558};
559#define CAICOS_CGCG_CGLS_ENABLE_LENGTH sizeof(caicos_cgcg_cgls_enable) / (3 * sizeof(u32))
560
561static const u32 caicos_mgcg_default[] =
562{
563 0x0000802c, 0xc0000000, 0xffffffff,
564 0x00005448, 0x00000100, 0xffffffff,
565 0x000055e4, 0x00600100, 0xffffffff,
566 0x0000160c, 0x00000100, 0xffffffff,
567 0x0000c164, 0x00000100, 0xffffffff,
568 0x00008a18, 0x00000100, 0xffffffff,
569 0x0000897c, 0x06000100, 0xffffffff,
570 0x00008b28, 0x00000100, 0xffffffff,
571 0x00009144, 0x00000100, 0xffffffff,
572 0x00009a60, 0x00000100, 0xffffffff,
573 0x00009868, 0x00000100, 0xffffffff,
574 0x00008d58, 0x00000100, 0xffffffff,
575 0x00009510, 0x00000100, 0xffffffff,
576 0x0000949c, 0x00000100, 0xffffffff,
577 0x00009654, 0x00000100, 0xffffffff,
578 0x00009030, 0x00000100, 0xffffffff,
579 0x00009034, 0x00000100, 0xffffffff,
580 0x00009038, 0x00000100, 0xffffffff,
581 0x0000903c, 0x00000100, 0xffffffff,
582 0x00009040, 0x00000100, 0xffffffff,
583 0x0000a200, 0x00000100, 0xffffffff,
584 0x0000a204, 0x00000100, 0xffffffff,
585 0x0000a208, 0x00000100, 0xffffffff,
586 0x0000a20c, 0x00000100, 0xffffffff,
587 0x0000977c, 0x00000100, 0xffffffff,
588 0x00003f80, 0x00000100, 0xffffffff,
589 0x0000a210, 0x00000100, 0xffffffff,
590 0x0000a214, 0x00000100, 0xffffffff,
591 0x000004d8, 0x00000100, 0xffffffff,
592 0x00009784, 0x00000100, 0xffffffff,
593 0x00009698, 0x00000100, 0xffffffff,
594 0x000004d4, 0x00000200, 0xffffffff,
595 0x000004d0, 0x00000000, 0xffffffff,
596 0x000030cc, 0x00000100, 0xffffffff,
597 0x0000d0c0, 0xff000100, 0xffffffff,
598 0x0000915c, 0x00010000, 0xffffffff,
599 0x00009160, 0x00030002, 0xffffffff,
600 0x00009164, 0x00050004, 0xffffffff,
601 0x00009168, 0x00070006, 0xffffffff,
602 0x00009178, 0x00070000, 0xffffffff,
603 0x0000917c, 0x00030002, 0xffffffff,
604 0x00009180, 0x00050004, 0xffffffff,
605 0x0000918c, 0x00010006, 0xffffffff,
606 0x00009190, 0x00090008, 0xffffffff,
607 0x00009194, 0x00070000, 0xffffffff,
608 0x00009198, 0x00030002, 0xffffffff,
609 0x0000919c, 0x00050004, 0xffffffff,
610 0x000091a8, 0x00010006, 0xffffffff,
611 0x000091ac, 0x00090008, 0xffffffff,
612 0x000091e8, 0x00000000, 0xffffffff,
613 0x00009294, 0x00000000, 0xffffffff,
614 0x000008f8, 0x00000010, 0xffffffff,
615 0x000008fc, 0x00000000, 0xffffffff,
616 0x000008f8, 0x00000011, 0xffffffff,
617 0x000008fc, 0x00000000, 0xffffffff,
618 0x000008f8, 0x00000012, 0xffffffff,
619 0x000008fc, 0x00000000, 0xffffffff,
620 0x000008f8, 0x00000013, 0xffffffff,
621 0x000008fc, 0x00000000, 0xffffffff,
622 0x000008f8, 0x00000014, 0xffffffff,
623 0x000008fc, 0x00000000, 0xffffffff,
624 0x000008f8, 0x00000015, 0xffffffff,
625 0x000008fc, 0x00000000, 0xffffffff,
626 0x000008f8, 0x00000016, 0xffffffff,
627 0x000008fc, 0x00000000, 0xffffffff,
628 0x000008f8, 0x00000017, 0xffffffff,
629 0x000008fc, 0x00000000, 0xffffffff,
630 0x000008f8, 0x00000018, 0xffffffff,
631 0x000008fc, 0x00000000, 0xffffffff,
632 0x000008f8, 0x00000019, 0xffffffff,
633 0x000008fc, 0x00000000, 0xffffffff,
634 0x000008f8, 0x0000001a, 0xffffffff,
635 0x000008fc, 0x00000000, 0xffffffff,
636 0x000008f8, 0x0000001b, 0xffffffff,
637 0x000008fc, 0x00000000, 0xffffffff
638};
639#define CAICOS_MGCG_DEFAULT_LENGTH sizeof(caicos_mgcg_default) / (3 * sizeof(u32))
640
641static const u32 caicos_mgcg_disable[] =
642{
643 0x0000802c, 0xc0000000, 0xffffffff,
644 0x000008f8, 0x00000000, 0xffffffff,
645 0x000008fc, 0xffffffff, 0xffffffff,
646 0x000008f8, 0x00000001, 0xffffffff,
647 0x000008fc, 0xffffffff, 0xffffffff,
648 0x000008f8, 0x00000002, 0xffffffff,
649 0x000008fc, 0xffffffff, 0xffffffff,
650 0x000008f8, 0x00000003, 0xffffffff,
651 0x000008fc, 0xffffffff, 0xffffffff,
652 0x00009150, 0x00600000, 0xffffffff
653};
654#define CAICOS_MGCG_DISABLE_LENGTH sizeof(caicos_mgcg_disable) / (3 * sizeof(u32))
655
656static const u32 caicos_mgcg_enable[] =
657{
658 0x0000802c, 0xc0000000, 0xffffffff,
659 0x000008f8, 0x00000000, 0xffffffff,
660 0x000008fc, 0x00000000, 0xffffffff,
661 0x000008f8, 0x00000001, 0xffffffff,
662 0x000008fc, 0x00000000, 0xffffffff,
663 0x000008f8, 0x00000002, 0xffffffff,
664 0x000008fc, 0x00000000, 0xffffffff,
665 0x000008f8, 0x00000003, 0xffffffff,
666 0x000008fc, 0x00000000, 0xffffffff,
667 0x00009150, 0x46944040, 0xffffffff
668};
669#define CAICOS_MGCG_ENABLE_LENGTH sizeof(caicos_mgcg_enable) / (3 * sizeof(u32))
670
671//********* TURKS **************//
672static const u32 turks_cgcg_cgls_default[] =
673{
674 0x000008f8, 0x00000010, 0xffffffff,
675 0x000008fc, 0x00000000, 0xffffffff,
676 0x000008f8, 0x00000011, 0xffffffff,
677 0x000008fc, 0x00000000, 0xffffffff,
678 0x000008f8, 0x00000012, 0xffffffff,
679 0x000008fc, 0x00000000, 0xffffffff,
680 0x000008f8, 0x00000013, 0xffffffff,
681 0x000008fc, 0x00000000, 0xffffffff,
682 0x000008f8, 0x00000014, 0xffffffff,
683 0x000008fc, 0x00000000, 0xffffffff,
684 0x000008f8, 0x00000015, 0xffffffff,
685 0x000008fc, 0x00000000, 0xffffffff,
686 0x000008f8, 0x00000016, 0xffffffff,
687 0x000008fc, 0x00000000, 0xffffffff,
688 0x000008f8, 0x00000017, 0xffffffff,
689 0x000008fc, 0x00000000, 0xffffffff,
690 0x000008f8, 0x00000018, 0xffffffff,
691 0x000008fc, 0x00000000, 0xffffffff,
692 0x000008f8, 0x00000019, 0xffffffff,
693 0x000008fc, 0x00000000, 0xffffffff,
694 0x000008f8, 0x0000001a, 0xffffffff,
695 0x000008fc, 0x00000000, 0xffffffff,
696 0x000008f8, 0x0000001b, 0xffffffff,
697 0x000008fc, 0x00000000, 0xffffffff,
698 0x000008f8, 0x00000020, 0xffffffff,
699 0x000008fc, 0x00000000, 0xffffffff,
700 0x000008f8, 0x00000021, 0xffffffff,
701 0x000008fc, 0x00000000, 0xffffffff,
702 0x000008f8, 0x00000022, 0xffffffff,
703 0x000008fc, 0x00000000, 0xffffffff,
704 0x000008f8, 0x00000023, 0xffffffff,
705 0x000008fc, 0x00000000, 0xffffffff,
706 0x000008f8, 0x00000024, 0xffffffff,
707 0x000008fc, 0x00000000, 0xffffffff,
708 0x000008f8, 0x00000025, 0xffffffff,
709 0x000008fc, 0x00000000, 0xffffffff,
710 0x000008f8, 0x00000026, 0xffffffff,
711 0x000008fc, 0x00000000, 0xffffffff,
712 0x000008f8, 0x00000027, 0xffffffff,
713 0x000008fc, 0x00000000, 0xffffffff,
714 0x000008f8, 0x00000028, 0xffffffff,
715 0x000008fc, 0x00000000, 0xffffffff,
716 0x000008f8, 0x00000029, 0xffffffff,
717 0x000008fc, 0x00000000, 0xffffffff,
718 0x000008f8, 0x0000002a, 0xffffffff,
719 0x000008fc, 0x00000000, 0xffffffff,
720 0x000008f8, 0x0000002b, 0xffffffff,
721 0x000008fc, 0x00000000, 0xffffffff
722};
723#define TURKS_CGCG_CGLS_DEFAULT_LENGTH sizeof(turks_cgcg_cgls_default) / (3 * sizeof(u32))
724
725static const u32 turks_cgcg_cgls_disable[] =
726{
727 0x000008f8, 0x00000010, 0xffffffff,
728 0x000008fc, 0xffffffff, 0xffffffff,
729 0x000008f8, 0x00000011, 0xffffffff,
730 0x000008fc, 0xffffffff, 0xffffffff,
731 0x000008f8, 0x00000012, 0xffffffff,
732 0x000008fc, 0xffffffff, 0xffffffff,
733 0x000008f8, 0x00000013, 0xffffffff,
734 0x000008fc, 0xffffffff, 0xffffffff,
735 0x000008f8, 0x00000014, 0xffffffff,
736 0x000008fc, 0xffffffff, 0xffffffff,
737 0x000008f8, 0x00000015, 0xffffffff,
738 0x000008fc, 0xffffffff, 0xffffffff,
739 0x000008f8, 0x00000016, 0xffffffff,
740 0x000008fc, 0xffffffff, 0xffffffff,
741 0x000008f8, 0x00000017, 0xffffffff,
742 0x000008fc, 0xffffffff, 0xffffffff,
743 0x000008f8, 0x00000018, 0xffffffff,
744 0x000008fc, 0xffffffff, 0xffffffff,
745 0x000008f8, 0x00000019, 0xffffffff,
746 0x000008fc, 0xffffffff, 0xffffffff,
747 0x000008f8, 0x0000001a, 0xffffffff,
748 0x000008fc, 0xffffffff, 0xffffffff,
749 0x000008f8, 0x0000001b, 0xffffffff,
750 0x000008fc, 0xffffffff, 0xffffffff,
751 0x000008f8, 0x00000020, 0xffffffff,
752 0x000008fc, 0x00000000, 0xffffffff,
753 0x000008f8, 0x00000021, 0xffffffff,
754 0x000008fc, 0x00000000, 0xffffffff,
755 0x000008f8, 0x00000022, 0xffffffff,
756 0x000008fc, 0x00000000, 0xffffffff,
757 0x000008f8, 0x00000023, 0xffffffff,
758 0x000008fc, 0x00000000, 0xffffffff,
759 0x000008f8, 0x00000024, 0xffffffff,
760 0x000008fc, 0x00000000, 0xffffffff,
761 0x000008f8, 0x00000025, 0xffffffff,
762 0x000008fc, 0x00000000, 0xffffffff,
763 0x000008f8, 0x00000026, 0xffffffff,
764 0x000008fc, 0x00000000, 0xffffffff,
765 0x000008f8, 0x00000027, 0xffffffff,
766 0x000008fc, 0x00000000, 0xffffffff,
767 0x000008f8, 0x00000028, 0xffffffff,
768 0x000008fc, 0x00000000, 0xffffffff,
769 0x000008f8, 0x00000029, 0xffffffff,
770 0x000008fc, 0x00000000, 0xffffffff,
771 0x000008f8, 0x0000002a, 0xffffffff,
772 0x000008fc, 0x00000000, 0xffffffff,
773 0x000008f8, 0x0000002b, 0xffffffff,
774 0x000008fc, 0x00000000, 0xffffffff,
775 0x00000644, 0x000f7912, 0x001f4180,
776 0x00000644, 0x000f3812, 0x001f4180
777};
778#define TURKS_CGCG_CGLS_DISABLE_LENGTH sizeof(turks_cgcg_cgls_disable) / (3 * sizeof(u32))
779
780static const u32 turks_cgcg_cgls_enable[] =
781{
782 /* 0x0000c124, 0x84180000, 0x00180000, */
783 0x00000644, 0x000f7892, 0x001f4080,
784 0x000008f8, 0x00000010, 0xffffffff,
785 0x000008fc, 0x00000000, 0xffffffff,
786 0x000008f8, 0x00000011, 0xffffffff,
787 0x000008fc, 0x00000000, 0xffffffff,
788 0x000008f8, 0x00000012, 0xffffffff,
789 0x000008fc, 0x00000000, 0xffffffff,
790 0x000008f8, 0x00000013, 0xffffffff,
791 0x000008fc, 0x00000000, 0xffffffff,
792 0x000008f8, 0x00000014, 0xffffffff,
793 0x000008fc, 0x00000000, 0xffffffff,
794 0x000008f8, 0x00000015, 0xffffffff,
795 0x000008fc, 0x00000000, 0xffffffff,
796 0x000008f8, 0x00000016, 0xffffffff,
797 0x000008fc, 0x00000000, 0xffffffff,
798 0x000008f8, 0x00000017, 0xffffffff,
799 0x000008fc, 0x00000000, 0xffffffff,
800 0x000008f8, 0x00000018, 0xffffffff,
801 0x000008fc, 0x00000000, 0xffffffff,
802 0x000008f8, 0x00000019, 0xffffffff,
803 0x000008fc, 0x00000000, 0xffffffff,
804 0x000008f8, 0x0000001a, 0xffffffff,
805 0x000008fc, 0x00000000, 0xffffffff,
806 0x000008f8, 0x0000001b, 0xffffffff,
807 0x000008fc, 0x00000000, 0xffffffff,
808 0x000008f8, 0x00000020, 0xffffffff,
809 0x000008fc, 0xffffffff, 0xffffffff,
810 0x000008f8, 0x00000021, 0xffffffff,
811 0x000008fc, 0xffffffff, 0xffffffff,
812 0x000008f8, 0x00000022, 0xffffffff,
813 0x000008fc, 0xffffffff, 0xffffffff,
814 0x000008f8, 0x00000023, 0xffffffff,
815 0x000008fc, 0xffffffff, 0xffffffff,
816 0x000008f8, 0x00000024, 0xffffffff,
817 0x000008fc, 0xffffffff, 0xffffffff,
818 0x000008f8, 0x00000025, 0xffffffff,
819 0x000008fc, 0xffffffff, 0xffffffff,
820 0x000008f8, 0x00000026, 0xffffffff,
821 0x000008fc, 0xffffffff, 0xffffffff,
822 0x000008f8, 0x00000027, 0xffffffff,
823 0x000008fc, 0xffffffff, 0xffffffff,
824 0x000008f8, 0x00000028, 0xffffffff,
825 0x000008fc, 0xffffffff, 0xffffffff,
826 0x000008f8, 0x00000029, 0xffffffff,
827 0x000008fc, 0xffffffff, 0xffffffff,
828 0x000008f8, 0x0000002a, 0xffffffff,
829 0x000008fc, 0xffffffff, 0xffffffff,
830 0x000008f8, 0x0000002b, 0xffffffff,
831 0x000008fc, 0xffffffff, 0xffffffff
832};
833#define TURKS_CGCG_CGLS_ENABLE_LENGTH sizeof(turks_cgcg_cgls_enable) / (3 * sizeof(u32))
834
835// These are the sequences for turks_mgcg_shls
836static const u32 turks_mgcg_default[] =
837{
838 0x0000802c, 0xc0000000, 0xffffffff,
839 0x00005448, 0x00000100, 0xffffffff,
840 0x000055e4, 0x00600100, 0xffffffff,
841 0x0000160c, 0x00000100, 0xffffffff,
842 0x0000c164, 0x00000100, 0xffffffff,
843 0x00008a18, 0x00000100, 0xffffffff,
844 0x0000897c, 0x06000100, 0xffffffff,
845 0x00008b28, 0x00000100, 0xffffffff,
846 0x00009144, 0x00000100, 0xffffffff,
847 0x00009a60, 0x00000100, 0xffffffff,
848 0x00009868, 0x00000100, 0xffffffff,
849 0x00008d58, 0x00000100, 0xffffffff,
850 0x00009510, 0x00000100, 0xffffffff,
851 0x0000949c, 0x00000100, 0xffffffff,
852 0x00009654, 0x00000100, 0xffffffff,
853 0x00009030, 0x00000100, 0xffffffff,
854 0x00009034, 0x00000100, 0xffffffff,
855 0x00009038, 0x00000100, 0xffffffff,
856 0x0000903c, 0x00000100, 0xffffffff,
857 0x00009040, 0x00000100, 0xffffffff,
858 0x0000a200, 0x00000100, 0xffffffff,
859 0x0000a204, 0x00000100, 0xffffffff,
860 0x0000a208, 0x00000100, 0xffffffff,
861 0x0000a20c, 0x00000100, 0xffffffff,
862 0x0000977c, 0x00000100, 0xffffffff,
863 0x00003f80, 0x00000100, 0xffffffff,
864 0x0000a210, 0x00000100, 0xffffffff,
865 0x0000a214, 0x00000100, 0xffffffff,
866 0x000004d8, 0x00000100, 0xffffffff,
867 0x00009784, 0x00000100, 0xffffffff,
868 0x00009698, 0x00000100, 0xffffffff,
869 0x000004d4, 0x00000200, 0xffffffff,
870 0x000004d0, 0x00000000, 0xffffffff,
871 0x000030cc, 0x00000100, 0xffffffff,
872 0x0000d0c0, 0x00000100, 0xffffffff,
873 0x0000915c, 0x00010000, 0xffffffff,
874 0x00009160, 0x00030002, 0xffffffff,
875 0x00009164, 0x00050004, 0xffffffff,
876 0x00009168, 0x00070006, 0xffffffff,
877 0x00009178, 0x00070000, 0xffffffff,
878 0x0000917c, 0x00030002, 0xffffffff,
879 0x00009180, 0x00050004, 0xffffffff,
880 0x0000918c, 0x00010006, 0xffffffff,
881 0x00009190, 0x00090008, 0xffffffff,
882 0x00009194, 0x00070000, 0xffffffff,
883 0x00009198, 0x00030002, 0xffffffff,
884 0x0000919c, 0x00050004, 0xffffffff,
885 0x000091a8, 0x00010006, 0xffffffff,
886 0x000091ac, 0x00090008, 0xffffffff,
887 0x000091b0, 0x00070000, 0xffffffff,
888 0x000091b4, 0x00030002, 0xffffffff,
889 0x000091b8, 0x00050004, 0xffffffff,
890 0x000091c4, 0x00010006, 0xffffffff,
891 0x000091c8, 0x00090008, 0xffffffff,
892 0x000091cc, 0x00070000, 0xffffffff,
893 0x000091d0, 0x00030002, 0xffffffff,
894 0x000091d4, 0x00050004, 0xffffffff,
895 0x000091e0, 0x00010006, 0xffffffff,
896 0x000091e4, 0x00090008, 0xffffffff,
897 0x000091e8, 0x00000000, 0xffffffff,
898 0x000091ec, 0x00070000, 0xffffffff,
899 0x000091f0, 0x00030002, 0xffffffff,
900 0x000091f4, 0x00050004, 0xffffffff,
901 0x00009200, 0x00010006, 0xffffffff,
902 0x00009204, 0x00090008, 0xffffffff,
903 0x00009208, 0x00070000, 0xffffffff,
904 0x0000920c, 0x00030002, 0xffffffff,
905 0x00009210, 0x00050004, 0xffffffff,
906 0x0000921c, 0x00010006, 0xffffffff,
907 0x00009220, 0x00090008, 0xffffffff,
908 0x00009294, 0x00000000, 0xffffffff,
909 0x000008f8, 0x00000010, 0xffffffff,
910 0x000008fc, 0x00000000, 0xffffffff,
911 0x000008f8, 0x00000011, 0xffffffff,
912 0x000008fc, 0x00000000, 0xffffffff,
913 0x000008f8, 0x00000012, 0xffffffff,
914 0x000008fc, 0x00000000, 0xffffffff,
915 0x000008f8, 0x00000013, 0xffffffff,
916 0x000008fc, 0x00000000, 0xffffffff,
917 0x000008f8, 0x00000014, 0xffffffff,
918 0x000008fc, 0x00000000, 0xffffffff,
919 0x000008f8, 0x00000015, 0xffffffff,
920 0x000008fc, 0x00000000, 0xffffffff,
921 0x000008f8, 0x00000016, 0xffffffff,
922 0x000008fc, 0x00000000, 0xffffffff,
923 0x000008f8, 0x00000017, 0xffffffff,
924 0x000008fc, 0x00000000, 0xffffffff,
925 0x000008f8, 0x00000018, 0xffffffff,
926 0x000008fc, 0x00000000, 0xffffffff,
927 0x000008f8, 0x00000019, 0xffffffff,
928 0x000008fc, 0x00000000, 0xffffffff,
929 0x000008f8, 0x0000001a, 0xffffffff,
930 0x000008fc, 0x00000000, 0xffffffff,
931 0x000008f8, 0x0000001b, 0xffffffff,
932 0x000008fc, 0x00000000, 0xffffffff
933};
934#define TURKS_MGCG_DEFAULT_LENGTH sizeof(turks_mgcg_default) / (3 * sizeof(u32))
935
936static const u32 turks_mgcg_disable[] =
937{
938 0x0000802c, 0xc0000000, 0xffffffff,
939 0x000008f8, 0x00000000, 0xffffffff,
940 0x000008fc, 0xffffffff, 0xffffffff,
941 0x000008f8, 0x00000001, 0xffffffff,
942 0x000008fc, 0xffffffff, 0xffffffff,
943 0x000008f8, 0x00000002, 0xffffffff,
944 0x000008fc, 0xffffffff, 0xffffffff,
945 0x000008f8, 0x00000003, 0xffffffff,
946 0x000008fc, 0xffffffff, 0xffffffff,
947 0x00009150, 0x00600000, 0xffffffff
948};
949#define TURKS_MGCG_DISABLE_LENGTH sizeof(turks_mgcg_disable) / (3 * sizeof(u32))
950
951static const u32 turks_mgcg_enable[] =
952{
953 0x0000802c, 0xc0000000, 0xffffffff,
954 0x000008f8, 0x00000000, 0xffffffff,
955 0x000008fc, 0x00000000, 0xffffffff,
956 0x000008f8, 0x00000001, 0xffffffff,
957 0x000008fc, 0x00000000, 0xffffffff,
958 0x000008f8, 0x00000002, 0xffffffff,
959 0x000008fc, 0x00000000, 0xffffffff,
960 0x000008f8, 0x00000003, 0xffffffff,
961 0x000008fc, 0x00000000, 0xffffffff,
962 0x00009150, 0x6e944000, 0xffffffff
963};
964#define TURKS_MGCG_ENABLE_LENGTH sizeof(turks_mgcg_enable) / (3 * sizeof(u32))
965
966#endif
967
968#ifndef BTC_SYSLS_SEQUENCE
969#define BTC_SYSLS_SEQUENCE 100
970
971
972//********* BARTS **************//
973static const u32 barts_sysls_default[] =
974{
975 /* Register, Value, Mask bits */
976 0x000055e8, 0x00000000, 0xffffffff,
977 0x0000d0bc, 0x00000000, 0xffffffff,
978 0x000015c0, 0x000c1401, 0xffffffff,
979 0x0000264c, 0x000c0400, 0xffffffff,
980 0x00002648, 0x000c0400, 0xffffffff,
981 0x00002650, 0x000c0400, 0xffffffff,
982 0x000020b8, 0x000c0400, 0xffffffff,
983 0x000020bc, 0x000c0400, 0xffffffff,
984 0x000020c0, 0x000c0c80, 0xffffffff,
985 0x0000f4a0, 0x000000c0, 0xffffffff,
986 0x0000f4a4, 0x00680fff, 0xffffffff,
987 0x000004c8, 0x00000001, 0xffffffff,
988 0x000064ec, 0x00000000, 0xffffffff,
989 0x00000c7c, 0x00000000, 0xffffffff,
990 0x00006dfc, 0x00000000, 0xffffffff
991};
992#define BARTS_SYSLS_DEFAULT_LENGTH sizeof(barts_sysls_default) / (3 * sizeof(u32))
993
994static const u32 barts_sysls_disable[] =
995{
996 0x000055e8, 0x00000000, 0xffffffff,
997 0x0000d0bc, 0x00000000, 0xffffffff,
998 0x000015c0, 0x00041401, 0xffffffff,
999 0x0000264c, 0x00040400, 0xffffffff,
1000 0x00002648, 0x00040400, 0xffffffff,
1001 0x00002650, 0x00040400, 0xffffffff,
1002 0x000020b8, 0x00040400, 0xffffffff,
1003 0x000020bc, 0x00040400, 0xffffffff,
1004 0x000020c0, 0x00040c80, 0xffffffff,
1005 0x0000f4a0, 0x000000c0, 0xffffffff,
1006 0x0000f4a4, 0x00680000, 0xffffffff,
1007 0x000004c8, 0x00000001, 0xffffffff,
1008 0x000064ec, 0x00007ffd, 0xffffffff,
1009 0x00000c7c, 0x0000ff00, 0xffffffff,
1010 0x00006dfc, 0x0000007f, 0xffffffff
1011};
1012#define BARTS_SYSLS_DISABLE_LENGTH sizeof(barts_sysls_disable) / (3 * sizeof(u32))
1013
1014static const u32 barts_sysls_enable[] =
1015{
1016 0x000055e8, 0x00000001, 0xffffffff,
1017 0x0000d0bc, 0x00000100, 0xffffffff,
1018 0x000015c0, 0x000c1401, 0xffffffff,
1019 0x0000264c, 0x000c0400, 0xffffffff,
1020 0x00002648, 0x000c0400, 0xffffffff,
1021 0x00002650, 0x000c0400, 0xffffffff,
1022 0x000020b8, 0x000c0400, 0xffffffff,
1023 0x000020bc, 0x000c0400, 0xffffffff,
1024 0x000020c0, 0x000c0c80, 0xffffffff,
1025 0x0000f4a0, 0x000000c0, 0xffffffff,
1026 0x0000f4a4, 0x00680fff, 0xffffffff,
1027 0x000004c8, 0x00000000, 0xffffffff,
1028 0x000064ec, 0x00000000, 0xffffffff,
1029 0x00000c7c, 0x00000000, 0xffffffff,
1030 0x00006dfc, 0x00000000, 0xffffffff
1031};
1032#define BARTS_SYSLS_ENABLE_LENGTH sizeof(barts_sysls_enable) / (3 * sizeof(u32))
1033
1034//********* CAICOS **************//
1035static const u32 caicos_sysls_default[] =
1036{
1037 0x000055e8, 0x00000000, 0xffffffff,
1038 0x0000d0bc, 0x00000000, 0xffffffff,
1039 0x000015c0, 0x000c1401, 0xffffffff,
1040 0x0000264c, 0x000c0400, 0xffffffff,
1041 0x00002648, 0x000c0400, 0xffffffff,
1042 0x00002650, 0x000c0400, 0xffffffff,
1043 0x000020b8, 0x000c0400, 0xffffffff,
1044 0x000020bc, 0x000c0400, 0xffffffff,
1045 0x0000f4a0, 0x000000c0, 0xffffffff,
1046 0x0000f4a4, 0x00680fff, 0xffffffff,
1047 0x000004c8, 0x00000001, 0xffffffff,
1048 0x000064ec, 0x00000000, 0xffffffff,
1049 0x00000c7c, 0x00000000, 0xffffffff,
1050 0x00006dfc, 0x00000000, 0xffffffff
1051};
1052#define CAICOS_SYSLS_DEFAULT_LENGTH sizeof(caicos_sysls_default) / (3 * sizeof(u32))
1053
1054static const u32 caicos_sysls_disable[] =
1055{
1056 0x000055e8, 0x00000000, 0xffffffff,
1057 0x0000d0bc, 0x00000000, 0xffffffff,
1058 0x000015c0, 0x00041401, 0xffffffff,
1059 0x0000264c, 0x00040400, 0xffffffff,
1060 0x00002648, 0x00040400, 0xffffffff,
1061 0x00002650, 0x00040400, 0xffffffff,
1062 0x000020b8, 0x00040400, 0xffffffff,
1063 0x000020bc, 0x00040400, 0xffffffff,
1064 0x0000f4a0, 0x000000c0, 0xffffffff,
1065 0x0000f4a4, 0x00680000, 0xffffffff,
1066 0x000004c8, 0x00000001, 0xffffffff,
1067 0x000064ec, 0x00007ffd, 0xffffffff,
1068 0x00000c7c, 0x0000ff00, 0xffffffff,
1069 0x00006dfc, 0x0000007f, 0xffffffff
1070};
1071#define CAICOS_SYSLS_DISABLE_LENGTH sizeof(caicos_sysls_disable) / (3 * sizeof(u32))
1072
1073static const u32 caicos_sysls_enable[] =
1074{
1075 0x000055e8, 0x00000001, 0xffffffff,
1076 0x0000d0bc, 0x00000100, 0xffffffff,
1077 0x000015c0, 0x000c1401, 0xffffffff,
1078 0x0000264c, 0x000c0400, 0xffffffff,
1079 0x00002648, 0x000c0400, 0xffffffff,
1080 0x00002650, 0x000c0400, 0xffffffff,
1081 0x000020b8, 0x000c0400, 0xffffffff,
1082 0x000020bc, 0x000c0400, 0xffffffff,
1083 0x0000f4a0, 0x000000c0, 0xffffffff,
1084 0x0000f4a4, 0x00680fff, 0xffffffff,
1085 0x000064ec, 0x00000000, 0xffffffff,
1086 0x00000c7c, 0x00000000, 0xffffffff,
1087 0x00006dfc, 0x00000000, 0xffffffff,
1088 0x000004c8, 0x00000000, 0xffffffff
1089};
1090#define CAICOS_SYSLS_ENABLE_LENGTH sizeof(caicos_sysls_enable) / (3 * sizeof(u32))
1091
1092//********* TURKS **************//
1093static const u32 turks_sysls_default[] =
1094{
1095 0x000055e8, 0x00000000, 0xffffffff,
1096 0x0000d0bc, 0x00000000, 0xffffffff,
1097 0x000015c0, 0x000c1401, 0xffffffff,
1098 0x0000264c, 0x000c0400, 0xffffffff,
1099 0x00002648, 0x000c0400, 0xffffffff,
1100 0x00002650, 0x000c0400, 0xffffffff,
1101 0x000020b8, 0x000c0400, 0xffffffff,
1102 0x000020bc, 0x000c0400, 0xffffffff,
1103 0x000020c0, 0x000c0c80, 0xffffffff,
1104 0x0000f4a0, 0x000000c0, 0xffffffff,
1105 0x0000f4a4, 0x00680fff, 0xffffffff,
1106 0x000004c8, 0x00000001, 0xffffffff,
1107 0x000064ec, 0x00000000, 0xffffffff,
1108 0x00000c7c, 0x00000000, 0xffffffff,
1109 0x00006dfc, 0x00000000, 0xffffffff
1110};
1111#define TURKS_SYSLS_DEFAULT_LENGTH sizeof(turks_sysls_default) / (3 * sizeof(u32))
1112
1113static const u32 turks_sysls_disable[] =
1114{
1115 0x000055e8, 0x00000000, 0xffffffff,
1116 0x0000d0bc, 0x00000000, 0xffffffff,
1117 0x000015c0, 0x00041401, 0xffffffff,
1118 0x0000264c, 0x00040400, 0xffffffff,
1119 0x00002648, 0x00040400, 0xffffffff,
1120 0x00002650, 0x00040400, 0xffffffff,
1121 0x000020b8, 0x00040400, 0xffffffff,
1122 0x000020bc, 0x00040400, 0xffffffff,
1123 0x000020c0, 0x00040c80, 0xffffffff,
1124 0x0000f4a0, 0x000000c0, 0xffffffff,
1125 0x0000f4a4, 0x00680000, 0xffffffff,
1126 0x000004c8, 0x00000001, 0xffffffff,
1127 0x000064ec, 0x00007ffd, 0xffffffff,
1128 0x00000c7c, 0x0000ff00, 0xffffffff,
1129 0x00006dfc, 0x0000007f, 0xffffffff
1130};
1131#define TURKS_SYSLS_DISABLE_LENGTH sizeof(turks_sysls_disable) / (3 * sizeof(u32))
1132
1133static const u32 turks_sysls_enable[] =
1134{
1135 0x000055e8, 0x00000001, 0xffffffff,
1136 0x0000d0bc, 0x00000100, 0xffffffff,
1137 0x000015c0, 0x000c1401, 0xffffffff,
1138 0x0000264c, 0x000c0400, 0xffffffff,
1139 0x00002648, 0x000c0400, 0xffffffff,
1140 0x00002650, 0x000c0400, 0xffffffff,
1141 0x000020b8, 0x000c0400, 0xffffffff,
1142 0x000020bc, 0x000c0400, 0xffffffff,
1143 0x000020c0, 0x000c0c80, 0xffffffff,
1144 0x0000f4a0, 0x000000c0, 0xffffffff,
1145 0x0000f4a4, 0x00680fff, 0xffffffff,
1146 0x000004c8, 0x00000000, 0xffffffff,
1147 0x000064ec, 0x00000000, 0xffffffff,
1148 0x00000c7c, 0x00000000, 0xffffffff,
1149 0x00006dfc, 0x00000000, 0xffffffff
1150};
1151#define TURKS_SYSLS_ENABLE_LENGTH sizeof(turks_sysls_enable) / (3 * sizeof(u32))
1152
1153#endif
1154
1155static void btc_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
1156 bool enable)
1157{
1158 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1159 u32 tmp, bif;
1160
1161 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1162 if (enable) {
1163 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1164 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1165 if (!pi->boot_in_gen2) {
1166 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
1167 bif |= CG_CLIENT_REQ(0xd);
1168 WREG32(CG_BIF_REQ_AND_RSP, bif);
1169
1170 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
1171 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
1172 tmp |= LC_GEN2_EN_STRAP;
1173
1174 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1175 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
1176 udelay(10);
1177 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1178 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
1179 }
1180 }
1181 } else {
1182 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
1183 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1184 if (!pi->boot_in_gen2) {
1185 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
1186 bif |= CG_CLIENT_REQ(0xd);
1187 WREG32(CG_BIF_REQ_AND_RSP, bif);
1188
1189 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
1190 tmp &= ~LC_GEN2_EN_STRAP;
1191 }
1192 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
1193 }
1194 }
1195}
1196
1197static void btc_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1198 bool enable)
1199{
1200 btc_enable_bif_dynamic_pcie_gen2(rdev, enable);
1201
1202 if (enable)
1203 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
1204 else
1205 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
1206}
1207
1208static int btc_disable_ulv(struct radeon_device *rdev)
1209{
1210 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1211
1212 if (eg_pi->ulv.supported) {
1213 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) != PPSMC_Result_OK)
1214 return -EINVAL;
1215 }
1216 return 0;
1217}
1218
1219static int btc_populate_ulv_state(struct radeon_device *rdev,
1220 RV770_SMC_STATETABLE *table)
1221{
1222 int ret = -EINVAL;
1223 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1224 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl;
1225
1226 if (ulv_pl->vddc) {
1227 ret = cypress_convert_power_level_to_smc(rdev,
1228 ulv_pl,
1229 &table->ULVState.levels[0],
1230 PPSMC_DISPLAY_WATERMARK_LOW);
1231 if (ret == 0) {
1232 table->ULVState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1233 table->ULVState.levels[0].ACIndex = 1;
1234
1235 table->ULVState.levels[1] = table->ULVState.levels[0];
1236 table->ULVState.levels[2] = table->ULVState.levels[0];
1237
1238 table->ULVState.flags |= PPSMC_SWSTATE_FLAG_DC;
1239
1240 WREG32(CG_ULV_CONTROL, BTC_CGULVCONTROL_DFLT);
1241 WREG32(CG_ULV_PARAMETER, BTC_CGULVPARAMETER_DFLT);
1242 }
1243 }
1244
1245 return ret;
1246}
1247
1248static int btc_populate_smc_acpi_state(struct radeon_device *rdev,
1249 RV770_SMC_STATETABLE *table)
1250{
1251 int ret = cypress_populate_smc_acpi_state(rdev, table);
1252
1253 if (ret == 0) {
1254 table->ACPIState.levels[0].ACIndex = 0;
1255 table->ACPIState.levels[1].ACIndex = 0;
1256 table->ACPIState.levels[2].ACIndex = 0;
1257 }
1258
1259 return ret;
1260}
1261
1262static void btc_program_mgcg_hw_sequence(struct radeon_device *rdev,
1263 const u32 *sequence, u32 count)
1264{
1265 u32 i, length = count * 3;
1266 u32 tmp;
1267
1268 for (i = 0; i < length; i+=3) {
1269 tmp = RREG32(sequence[i]);
1270 tmp &= ~sequence[i+2];
1271 tmp |= sequence[i+1] & sequence[i+2];
1272 WREG32(sequence[i], tmp);
1273 }
1274}
1275
1276static void btc_cg_clock_gating_default(struct radeon_device *rdev)
1277{
1278 u32 count;
1279 const u32 *p = NULL;
1280
1281 if (rdev->family == CHIP_BARTS) {
1282 p = (const u32 *)&barts_cgcg_cgls_default;
1283 count = BARTS_CGCG_CGLS_DEFAULT_LENGTH;
1284 } else if (rdev->family == CHIP_TURKS) {
1285 p = (const u32 *)&turks_cgcg_cgls_default;
1286 count = TURKS_CGCG_CGLS_DEFAULT_LENGTH;
1287 } else if (rdev->family == CHIP_CAICOS) {
1288 p = (const u32 *)&caicos_cgcg_cgls_default;
1289 count = CAICOS_CGCG_CGLS_DEFAULT_LENGTH;
1290 } else
1291 return;
1292
1293 btc_program_mgcg_hw_sequence(rdev, p, count);
1294}
1295
1296static void btc_cg_clock_gating_enable(struct radeon_device *rdev,
1297 bool enable)
1298{
1299 u32 count;
1300 const u32 *p = NULL;
1301
1302 if (enable) {
1303 if (rdev->family == CHIP_BARTS) {
1304 p = (const u32 *)&barts_cgcg_cgls_enable;
1305 count = BARTS_CGCG_CGLS_ENABLE_LENGTH;
1306 } else if (rdev->family == CHIP_TURKS) {
1307 p = (const u32 *)&turks_cgcg_cgls_enable;
1308 count = TURKS_CGCG_CGLS_ENABLE_LENGTH;
1309 } else if (rdev->family == CHIP_CAICOS) {
1310 p = (const u32 *)&caicos_cgcg_cgls_enable;
1311 count = CAICOS_CGCG_CGLS_ENABLE_LENGTH;
1312 } else
1313 return;
1314 } else {
1315 if (rdev->family == CHIP_BARTS) {
1316 p = (const u32 *)&barts_cgcg_cgls_disable;
1317 count = BARTS_CGCG_CGLS_DISABLE_LENGTH;
1318 } else if (rdev->family == CHIP_TURKS) {
1319 p = (const u32 *)&turks_cgcg_cgls_disable;
1320 count = TURKS_CGCG_CGLS_DISABLE_LENGTH;
1321 } else if (rdev->family == CHIP_CAICOS) {
1322 p = (const u32 *)&caicos_cgcg_cgls_disable;
1323 count = CAICOS_CGCG_CGLS_DISABLE_LENGTH;
1324 } else
1325 return;
1326 }
1327
1328 btc_program_mgcg_hw_sequence(rdev, p, count);
1329}
1330
1331static void btc_mg_clock_gating_default(struct radeon_device *rdev)
1332{
1333 u32 count;
1334 const u32 *p = NULL;
1335
1336 if (rdev->family == CHIP_BARTS) {
1337 p = (const u32 *)&barts_mgcg_default;
1338 count = BARTS_MGCG_DEFAULT_LENGTH;
1339 } else if (rdev->family == CHIP_TURKS) {
1340 p = (const u32 *)&turks_mgcg_default;
1341 count = TURKS_MGCG_DEFAULT_LENGTH;
1342 } else if (rdev->family == CHIP_CAICOS) {
1343 p = (const u32 *)&caicos_mgcg_default;
1344 count = CAICOS_MGCG_DEFAULT_LENGTH;
1345 } else
1346 return;
1347
1348 btc_program_mgcg_hw_sequence(rdev, p, count);
1349}
1350
1351static void btc_mg_clock_gating_enable(struct radeon_device *rdev,
1352 bool enable)
1353{
1354 u32 count;
1355 const u32 *p = NULL;
1356
1357 if (enable) {
1358 if (rdev->family == CHIP_BARTS) {
1359 p = (const u32 *)&barts_mgcg_enable;
1360 count = BARTS_MGCG_ENABLE_LENGTH;
1361 } else if (rdev->family == CHIP_TURKS) {
1362 p = (const u32 *)&turks_mgcg_enable;
1363 count = TURKS_MGCG_ENABLE_LENGTH;
1364 } else if (rdev->family == CHIP_CAICOS) {
1365 p = (const u32 *)&caicos_mgcg_enable;
1366 count = CAICOS_MGCG_ENABLE_LENGTH;
1367 } else
1368 return;
1369 } else {
1370 if (rdev->family == CHIP_BARTS) {
1371 p = (const u32 *)&barts_mgcg_disable[0];
1372 count = BARTS_MGCG_DISABLE_LENGTH;
1373 } else if (rdev->family == CHIP_TURKS) {
1374 p = (const u32 *)&turks_mgcg_disable[0];
1375 count = TURKS_MGCG_DISABLE_LENGTH;
1376 } else if (rdev->family == CHIP_CAICOS) {
1377 p = (const u32 *)&caicos_mgcg_disable[0];
1378 count = CAICOS_MGCG_DISABLE_LENGTH;
1379 } else
1380 return;
1381 }
1382
1383 btc_program_mgcg_hw_sequence(rdev, p, count);
1384}
1385
1386static void btc_ls_clock_gating_default(struct radeon_device *rdev)
1387{
1388 u32 count;
1389 const u32 *p = NULL;
1390
1391 if (rdev->family == CHIP_BARTS) {
1392 p = (const u32 *)&barts_sysls_default;
1393 count = BARTS_SYSLS_DEFAULT_LENGTH;
1394 } else if (rdev->family == CHIP_TURKS) {
1395 p = (const u32 *)&turks_sysls_default;
1396 count = TURKS_SYSLS_DEFAULT_LENGTH;
1397 } else if (rdev->family == CHIP_CAICOS) {
1398 p = (const u32 *)&caicos_sysls_default;
1399 count = CAICOS_SYSLS_DEFAULT_LENGTH;
1400 } else
1401 return;
1402
1403 btc_program_mgcg_hw_sequence(rdev, p, count);
1404}
1405
1406static void btc_ls_clock_gating_enable(struct radeon_device *rdev,
1407 bool enable)
1408{
1409 u32 count;
1410 const u32 *p = NULL;
1411
1412 if (enable) {
1413 if (rdev->family == CHIP_BARTS) {
1414 p = (const u32 *)&barts_sysls_enable;
1415 count = BARTS_SYSLS_ENABLE_LENGTH;
1416 } else if (rdev->family == CHIP_TURKS) {
1417 p = (const u32 *)&turks_sysls_enable;
1418 count = TURKS_SYSLS_ENABLE_LENGTH;
1419 } else if (rdev->family == CHIP_CAICOS) {
1420 p = (const u32 *)&caicos_sysls_enable;
1421 count = CAICOS_SYSLS_ENABLE_LENGTH;
1422 } else
1423 return;
1424 } else {
1425 if (rdev->family == CHIP_BARTS) {
1426 p = (const u32 *)&barts_sysls_disable;
1427 count = BARTS_SYSLS_DISABLE_LENGTH;
1428 } else if (rdev->family == CHIP_TURKS) {
1429 p = (const u32 *)&turks_sysls_disable;
1430 count = TURKS_SYSLS_DISABLE_LENGTH;
1431 } else if (rdev->family == CHIP_CAICOS) {
1432 p = (const u32 *)&caicos_sysls_disable;
1433 count = CAICOS_SYSLS_DISABLE_LENGTH;
1434 } else
1435 return;
1436 }
1437
1438 btc_program_mgcg_hw_sequence(rdev, p, count);
1439}
1440
1441static bool btc_dpm_enabled(struct radeon_device *rdev)
1442{
1443 if (rv770_is_smc_running(rdev))
1444 return true;
1445 else
1446 return false;
1447}
1448
1449static int btc_init_smc_table(struct radeon_device *rdev)
1450{
1451 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1452 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1453 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1454 RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1455 int ret;
1456
1457 memset(table, 0, sizeof(RV770_SMC_STATETABLE));
1458
1459 cypress_populate_smc_voltage_tables(rdev, table);
1460
1461 switch (rdev->pm.int_thermal_type) {
1462 case THERMAL_TYPE_EVERGREEN:
1463 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1464 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1465 break;
1466 case THERMAL_TYPE_NONE:
1467 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1468 break;
1469 default:
1470 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1471 break;
1472 }
1473
1474 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1475 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1476
1477 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1478 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1479
1480 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1481 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1482
1483 if (pi->mem_gddr5)
1484 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1485
1486 ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1487 if (ret)
1488 return ret;
1489
1490 if (eg_pi->sclk_deep_sleep)
1491 WREG32_P(SCLK_PSKIP_CNTL, PSKIP_ON_ALLOW_STOP_HI(32),
1492 ~PSKIP_ON_ALLOW_STOP_HI_MASK);
1493
1494 ret = btc_populate_smc_acpi_state(rdev, table);
1495 if (ret)
1496 return ret;
1497
1498 if (eg_pi->ulv.supported) {
1499 ret = btc_populate_ulv_state(rdev, table);
1500 if (ret)
1501 eg_pi->ulv.supported = false;
1502 }
1503
1504 table->driverState = table->initialState;
1505
1506 return rv770_copy_bytes_to_smc(rdev,
1507 pi->state_table_start,
1508 (u8 *)table,
1509 sizeof(RV770_SMC_STATETABLE),
1510 pi->sram_end);
1511}
1512
1513static int btc_reset_to_default(struct radeon_device *rdev)
1514{
1515 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) != PPSMC_Result_OK)
1516 return -EINVAL;
1517
1518 return 0;
1519}
1520
1521static void btc_stop_smc(struct radeon_device *rdev)
1522{
1523 int i;
1524
1525 for (i = 0; i < rdev->usec_timeout; i++) {
1526 if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1)
1527 break;
1528 udelay(1);
1529 }
1530 udelay(100);
1531
1532 r7xx_stop_smc(rdev);
1533}
1534
1535static void btc_read_arb_registers(struct radeon_device *rdev)
1536{
1537 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1538 struct evergreen_arb_registers *arb_registers =
1539 &eg_pi->bootup_arb_registers;
1540
1541 arb_registers->mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
1542 arb_registers->mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
1543 arb_registers->mc_arb_rfsh_rate = RREG32(MC_ARB_RFSH_RATE);
1544 arb_registers->mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
1545}
1546
1547
1548static void btc_set_arb0_registers(struct radeon_device *rdev,
1549 struct evergreen_arb_registers *arb_registers)
1550{
1551 u32 val;
1552
1553 WREG32(MC_ARB_DRAM_TIMING, arb_registers->mc_arb_dram_timing);
1554 WREG32(MC_ARB_DRAM_TIMING2, arb_registers->mc_arb_dram_timing2);
1555
1556 val = (arb_registers->mc_arb_rfsh_rate & POWERMODE0_MASK) >>
1557 POWERMODE0_SHIFT;
1558 WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);
1559
1560 val = (arb_registers->mc_arb_burst_time & STATE0_MASK) >>
1561 STATE0_SHIFT;
1562 WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);
1563}
1564
1565static void btc_set_boot_state_timing(struct radeon_device *rdev)
1566{
1567 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1568
1569 if (eg_pi->ulv.supported)
1570 btc_set_arb0_registers(rdev, &eg_pi->bootup_arb_registers);
1571}
1572
1573static bool btc_is_state_ulv_compatible(struct radeon_device *rdev,
1574 struct radeon_ps *radeon_state)
1575{
1576 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
1577 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1578 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl;
1579
1580 if (state->low.mclk != ulv_pl->mclk)
1581 return false;
1582
1583 if (state->low.vddci != ulv_pl->vddci)
1584 return false;
1585
1586 /* XXX check minclocks, etc. */
1587
1588 return true;
1589}
1590
1591
1592static int btc_set_ulv_dram_timing(struct radeon_device *rdev)
1593{
1594 u32 val;
1595 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1596 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl;
1597
1598 radeon_atom_set_engine_dram_timings(rdev,
1599 ulv_pl->sclk,
1600 ulv_pl->mclk);
1601
1602 val = rv770_calculate_memory_refresh_rate(rdev, ulv_pl->sclk);
1603 WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);
1604
1605 val = cypress_calculate_burst_time(rdev, ulv_pl->sclk, ulv_pl->mclk);
1606 WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);
1607
1608 return 0;
1609}
1610
1611static int btc_enable_ulv(struct radeon_device *rdev)
1612{
1613 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) != PPSMC_Result_OK)
1614 return -EINVAL;
1615
1616 return 0;
1617}
1618
1619static int btc_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev)
1620{
1621 int ret = 0;
1622 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1623 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
1624
1625 if (eg_pi->ulv.supported) {
1626 if (btc_is_state_ulv_compatible(rdev, radeon_new_state)) {
1627 // Set ARB[0] to reflect the DRAM timing needed for ULV.
1628 ret = btc_set_ulv_dram_timing(rdev);
1629 if (ret == 0)
1630 ret = btc_enable_ulv(rdev);
1631 }
1632 }
1633
1634 return ret;
1635}
1636
1637static bool btc_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
1638{
1639 bool result = true;
1640
1641 switch (in_reg) {
1642 case MC_SEQ_RAS_TIMING >> 2:
1643 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
1644 break;
1645 case MC_SEQ_CAS_TIMING >> 2:
1646 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
1647 break;
1648 case MC_SEQ_MISC_TIMING >> 2:
1649 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
1650 break;
1651 case MC_SEQ_MISC_TIMING2 >> 2:
1652 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
1653 break;
1654 case MC_SEQ_RD_CTL_D0 >> 2:
1655 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
1656 break;
1657 case MC_SEQ_RD_CTL_D1 >> 2:
1658 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
1659 break;
1660 case MC_SEQ_WR_CTL_D0 >> 2:
1661 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
1662 break;
1663 case MC_SEQ_WR_CTL_D1 >> 2:
1664 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
1665 break;
1666 case MC_PMG_CMD_EMRS >> 2:
1667 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1668 break;
1669 case MC_PMG_CMD_MRS >> 2:
1670 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1671 break;
1672 case MC_PMG_CMD_MRS1 >> 2:
1673 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1674 break;
1675 default:
1676 result = false;
1677 break;
1678 }
1679
1680 return result;
1681}
1682
1683static void btc_set_valid_flag(struct evergreen_mc_reg_table *table)
1684{
1685 u8 i, j;
1686
1687 for (i = 0; i < table->last; i++) {
1688 for (j = 1; j < table->num_entries; j++) {
1689 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
1690 table->mc_reg_table_entry[j].mc_data[i]) {
1691 table->valid_flag |= (1 << i);
1692 break;
1693 }
1694 }
1695 }
1696}
1697
1698static int btc_set_mc_special_registers(struct radeon_device *rdev,
1699 struct evergreen_mc_reg_table *table)
1700{
1701 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1702 u8 i, j, k;
1703 u32 tmp;
1704
1705 for (i = 0, j = table->last; i < table->last; i++) {
1706 switch (table->mc_reg_address[i].s1) {
1707 case MC_SEQ_MISC1 >> 2:
1708 tmp = RREG32(MC_PMG_CMD_EMRS);
1709 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
1710 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1711 for (k = 0; k < table->num_entries; k++) {
1712 table->mc_reg_table_entry[k].mc_data[j] =
1713 ((tmp & 0xffff0000)) |
1714 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
1715 }
1716 j++;
1717
1718 if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1719 return -EINVAL;
1720
1721 tmp = RREG32(MC_PMG_CMD_MRS);
1722 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
1723 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1724 for (k = 0; k < table->num_entries; k++) {
1725 table->mc_reg_table_entry[k].mc_data[j] =
1726 (tmp & 0xffff0000) |
1727 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
1728 if (!pi->mem_gddr5)
1729 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
1730 }
1731 j++;
1732
1733 if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1734 return -EINVAL;
1735 break;
1736 case MC_SEQ_RESERVE_M >> 2:
1737 tmp = RREG32(MC_PMG_CMD_MRS1);
1738 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
1739 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1740 for (k = 0; k < table->num_entries; k++) {
1741 table->mc_reg_table_entry[k].mc_data[j] =
1742 (tmp & 0xffff0000) |
1743 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
1744 }
1745 j++;
1746
1747 if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1748 return -EINVAL;
1749 break;
1750 default:
1751 break;
1752 }
1753 }
1754
1755 table->last = j;
1756
1757 return 0;
1758}
1759
1760static void btc_set_s0_mc_reg_index(struct evergreen_mc_reg_table *table)
1761{
1762 u32 i;
1763 u16 address;
1764
1765 for (i = 0; i < table->last; i++) {
1766 table->mc_reg_address[i].s0 =
1767 btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
1768 address : table->mc_reg_address[i].s1;
1769 }
1770}
1771
1772static int btc_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
1773 struct evergreen_mc_reg_table *eg_table)
1774{
1775 u8 i, j;
1776
1777 if (table->last > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1778 return -EINVAL;
1779
1780 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
1781 return -EINVAL;
1782
1783 for (i = 0; i < table->last; i++)
1784 eg_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
1785 eg_table->last = table->last;
1786
1787 for (i = 0; i < table->num_entries; i++) {
1788 eg_table->mc_reg_table_entry[i].mclk_max =
1789 table->mc_reg_table_entry[i].mclk_max;
1790 for(j = 0; j < table->last; j++)
1791 eg_table->mc_reg_table_entry[i].mc_data[j] =
1792 table->mc_reg_table_entry[i].mc_data[j];
1793 }
1794 eg_table->num_entries = table->num_entries;
1795
1796 return 0;
1797}
1798
1799static int btc_initialize_mc_reg_table(struct radeon_device *rdev)
1800{
1801 int ret;
1802 struct atom_mc_reg_table *table;
1803 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1804 struct evergreen_mc_reg_table *eg_table = &eg_pi->mc_reg_table;
1805 u8 module_index = rv770_get_memory_module_index(rdev);
1806
1807 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
1808 if (!table)
1809 return -ENOMEM;
1810
1811 /* Program additional LP registers that are no longer programmed by VBIOS */
1812 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
1813 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
1814 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
1815 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
1816 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
1817 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
1818 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
1819 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
1820 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
1821 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
1822 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
1823
1824 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
1825
1826 if (ret)
1827 goto init_mc_done;
1828
1829 ret = btc_copy_vbios_mc_reg_table(table, eg_table);
1830
1831 if (ret)
1832 goto init_mc_done;
1833
1834 btc_set_s0_mc_reg_index(eg_table);
1835 ret = btc_set_mc_special_registers(rdev, eg_table);
1836
1837 if (ret)
1838 goto init_mc_done;
1839
1840 btc_set_valid_flag(eg_table);
1841
1842init_mc_done:
1843 kfree(table);
1844
1845 return ret;
1846}
1847
1848static void btc_init_stutter_mode(struct radeon_device *rdev)
1849{
1850 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1851 u32 tmp;
1852
1853 if (pi->mclk_stutter_mode_threshold) {
1854 if (pi->mem_gddr5) {
1855 tmp = RREG32(MC_PMG_AUTO_CFG);
1856 if ((0x200 & tmp) == 0) {
1857 tmp = (tmp & 0xfffffc0b) | 0x204;
1858 WREG32(MC_PMG_AUTO_CFG, tmp);
1859 }
1860 }
1861 }
1862}
1863
1864void btc_dpm_reset_asic(struct radeon_device *rdev)
1865{
1866 rv770_restrict_performance_levels_before_switch(rdev);
1867 btc_disable_ulv(rdev);
1868 btc_set_boot_state_timing(rdev);
1869 rv770_set_boot_state(rdev);
1870}
1871
1872int btc_dpm_set_power_state(struct radeon_device *rdev)
1873{
1874 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1875
1876 btc_disable_ulv(rdev);
1877 btc_set_boot_state_timing(rdev);
1878 rv770_restrict_performance_levels_before_switch(rdev);
1879
1880 if (eg_pi->pcie_performance_request)
1881 cypress_notify_link_speed_change_before_state_change(rdev);
1882
1883 rv770_halt_smc(rdev);
1884 cypress_upload_sw_state(rdev);
1885
1886 if (eg_pi->dynamic_ac_timing)
1887 cypress_upload_mc_reg_table(rdev);
1888
1889 cypress_program_memory_timing_parameters(rdev);
1890
1891 rv770_resume_smc(rdev);
1892 rv770_set_sw_state(rdev);
1893
1894 if (eg_pi->pcie_performance_request)
1895 cypress_notify_link_speed_change_after_state_change(rdev);
1896
1897 btc_set_power_state_conditionally_enable_ulv(rdev);
1898
1899#if 0
1900 /* XXX */
1901 rv770_unrestrict_performance_levels_after_switch(rdev);
1902#endif
1903
1904 return 0;
1905}
1906
1907int btc_dpm_enable(struct radeon_device *rdev)
1908{
1909 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1910 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1911
1912 if (pi->gfx_clock_gating)
1913 btc_cg_clock_gating_default(rdev);
1914
1915 if (btc_dpm_enabled(rdev))
1916 return -EINVAL;
1917
1918 if (pi->mg_clock_gating)
1919 btc_mg_clock_gating_default(rdev);
1920
1921 if (eg_pi->ls_clock_gating)
1922 btc_ls_clock_gating_default(rdev);
1923
1924 if (pi->voltage_control) {
1925 rv770_enable_voltage_control(rdev, true);
1926 cypress_construct_voltage_tables(rdev);
1927 }
1928
1929 if (pi->mvdd_control)
1930 cypress_get_mvdd_configuration(rdev);
1931
1932 if (eg_pi->dynamic_ac_timing)
1933 btc_initialize_mc_reg_table(rdev);
1934
1935 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1936 rv770_enable_backbias(rdev, true);
1937
1938 if (pi->dynamic_ss)
1939 cypress_enable_spread_spectrum(rdev, true);
1940
1941 if (pi->thermal_protection)
1942 rv770_enable_thermal_protection(rdev, true);
1943
1944 rv770_setup_bsp(rdev);
1945 rv770_program_git(rdev);
1946 rv770_program_tp(rdev);
1947 rv770_program_tpp(rdev);
1948 rv770_program_sstp(rdev);
1949 rv770_program_engine_speed_parameters(rdev);
1950 cypress_enable_display_gap(rdev);
1951 rv770_program_vc(rdev);
1952
1953 if (pi->dynamic_pcie_gen2)
1954 btc_enable_dynamic_pcie_gen2(rdev, true);
1955
1956 if (rv770_upload_firmware(rdev))
1957 return -EINVAL;
1958
1959 cypress_get_table_locations(rdev);
1960 btc_init_smc_table(rdev);
1961
1962 if (eg_pi->dynamic_ac_timing)
1963 cypress_populate_mc_reg_table(rdev);
1964
1965 cypress_program_response_times(rdev);
1966 r7xx_start_smc(rdev);
1967 cypress_notify_smc_display_change(rdev, false);
1968 cypress_enable_sclk_control(rdev, true);
1969
1970 if (eg_pi->memory_transition)
1971 cypress_enable_mclk_control(rdev, true);
1972
1973 cypress_start_dpm(rdev);
1974
1975 if (pi->gfx_clock_gating)
1976 btc_cg_clock_gating_enable(rdev, true);
1977
1978 if (pi->mg_clock_gating)
1979 btc_mg_clock_gating_enable(rdev, true);
1980
1981 if (eg_pi->ls_clock_gating)
1982 btc_ls_clock_gating_enable(rdev, true);
1983
1984 if (rdev->irq.installed &&
1985 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1986 PPSMC_Result result;
1987
1988 rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1989 rdev->irq.dpm_thermal = true;
1990 radeon_irq_set(rdev);
1991 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
1992
1993 if (result != PPSMC_Result_OK)
1994 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1995 }
1996
1997 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1998
1999 btc_init_stutter_mode(rdev);
2000
2001 return 0;
2002};
2003
2004void btc_dpm_disable(struct radeon_device *rdev)
2005{
2006 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2007 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2008
2009 if (!btc_dpm_enabled(rdev))
2010 return;
2011
2012 rv770_clear_vc(rdev);
2013
2014 if (pi->thermal_protection)
2015 rv770_enable_thermal_protection(rdev, false);
2016
2017 if (pi->dynamic_pcie_gen2)
2018 btc_enable_dynamic_pcie_gen2(rdev, false);
2019
2020 if (rdev->irq.installed &&
2021 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
2022 rdev->irq.dpm_thermal = false;
2023 radeon_irq_set(rdev);
2024 }
2025
2026 if (pi->gfx_clock_gating)
2027 btc_cg_clock_gating_enable(rdev, false);
2028
2029 if (pi->mg_clock_gating)
2030 btc_mg_clock_gating_enable(rdev, false);
2031
2032 if (eg_pi->ls_clock_gating)
2033 btc_ls_clock_gating_enable(rdev, false);
2034
2035 rv770_stop_dpm(rdev);
2036 btc_reset_to_default(rdev);
2037 btc_stop_smc(rdev);
2038 cypress_enable_spread_spectrum(rdev, false);
2039}
2040
2041void btc_dpm_setup_asic(struct radeon_device *rdev)
2042{
2043 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2044
2045 rv770_get_memory_type(rdev);
2046 rv740_read_clock_registers(rdev);
2047 btc_read_arb_registers(rdev);
2048 rv770_read_voltage_smio_registers(rdev);
2049
2050 if (eg_pi->pcie_performance_request)
2051 cypress_advertise_gen2_capability(rdev);
2052
2053 rv770_get_pcie_gen2_status(rdev);
2054 rv770_enable_acpi_pm(rdev);
2055}
2056
2057int btc_dpm_init(struct radeon_device *rdev)
2058{
2059 struct rv7xx_power_info *pi;
2060 struct evergreen_power_info *eg_pi;
2061 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
2062 u16 data_offset, size;
2063 u8 frev, crev;
2064 struct atom_clock_dividers dividers;
2065 int ret;
2066
2067 eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL);
2068 if (eg_pi == NULL)
2069 return -ENOMEM;
2070 rdev->pm.dpm.priv = eg_pi;
2071 pi = &eg_pi->rv7xx;
2072
2073 rv770_get_max_vddc(rdev);
2074
2075 eg_pi->ulv.supported = false;
2076 pi->acpi_vddc = 0;
2077 eg_pi->acpi_vddci = 0;
2078 pi->min_vddc_in_table = 0;
2079 pi->max_vddc_in_table = 0;
2080
2081 ret = rv7xx_parse_power_table(rdev);
2082 if (ret)
2083 return ret;
2084
2085 if (rdev->pm.dpm.voltage_response_time == 0)
2086 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2087 if (rdev->pm.dpm.backbias_response_time == 0)
2088 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2089
2090 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2091 0, false, &dividers);
2092 if (ret)
2093 pi->ref_div = dividers.ref_div + 1;
2094 else
2095 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2096
2097 pi->mclk_strobe_mode_threshold = 40000;
2098 pi->mclk_edc_enable_threshold = 40000;
2099 eg_pi->mclk_edc_wr_enable_threshold = 40000;
2100
2101 pi->voltage_control =
2102 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);
2103
2104 pi->mvdd_control =
2105 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC);
2106
2107 eg_pi->vddci_control =
2108 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI);
2109
2110 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
2111 &frev, &crev, &data_offset)) {
2112 pi->sclk_ss = true;
2113 pi->mclk_ss = true;
2114 pi->dynamic_ss = true;
2115 } else {
2116 pi->sclk_ss = false;
2117 pi->mclk_ss = false;
2118 pi->dynamic_ss = true;
2119 }
2120
2121 pi->asi = RV770_ASI_DFLT;
2122 pi->pasi = CYPRESS_HASI_DFLT;
2123 pi->vrc = CYPRESS_VRC_DFLT;
2124
2125 pi->power_gating = false;
2126
2127 pi->gfx_clock_gating = true;
2128
2129 pi->mg_clock_gating = true;
2130 pi->mgcgtssm = true;
2131 eg_pi->ls_clock_gating = false;
2132 eg_pi->sclk_deep_sleep = false;
2133
2134 pi->dynamic_pcie_gen2 = true;
2135
2136 if (pi->gfx_clock_gating &&
2137 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
2138 pi->thermal_protection = true;
2139 else
2140 pi->thermal_protection = false;
2141
2142 pi->display_gap = true;
2143
2144 if (rdev->flags & RADEON_IS_MOBILITY)
2145 pi->dcodt = true;
2146 else
2147 pi->dcodt = false;
2148
2149 pi->ulps = true;
2150
2151 eg_pi->dynamic_ac_timing = true;
2152 eg_pi->abm = true;
2153 eg_pi->mcls = true;
2154 eg_pi->light_sleep = true;
2155 eg_pi->memory_transition = true;
2156#if defined(CONFIG_ACPI)
2157 eg_pi->pcie_performance_request =
2158 radeon_acpi_is_pcie_performance_request_supported(rdev);
2159#else
2160 eg_pi->pcie_performance_request = false;
2161#endif
2162
2163 if (rdev->family == CHIP_BARTS)
2164 eg_pi->dll_default_on = true;
2165 else
2166 eg_pi->dll_default_on = false;
2167
2168 eg_pi->sclk_deep_sleep = false;
2169 if (ASIC_IS_LOMBOK(rdev))
2170 pi->mclk_stutter_mode_threshold = 30000;
2171 else
2172 pi->mclk_stutter_mode_threshold = 0;
2173
2174 pi->sram_end = SMC_RAM_END;
2175
2176 return 0;
2177}
2178
2179void btc_dpm_fini(struct radeon_device *rdev)
2180{
2181 int i;
2182
2183 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2184 kfree(rdev->pm.dpm.ps[i].ps_priv);
2185 }
2186 kfree(rdev->pm.dpm.ps);
2187 kfree(rdev->pm.dpm.priv);
2188}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 17:12:07 -0400