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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/gpu/drm/radeon/atombios_crtc.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c766
1 files changed, 622 insertions, 144 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index c15287a590ff..a87990b3ae84 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -241,27 +241,31 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
241{ 241{
242 struct drm_device *dev = crtc->dev; 242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private; 243 struct radeon_device *rdev = dev->dev_private;
244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
244 245
245 switch (mode) { 246 switch (mode) {
246 case DRM_MODE_DPMS_ON: 247 case DRM_MODE_DPMS_ON:
247 atombios_enable_crtc(crtc, 1); 248 atombios_enable_crtc(crtc, ATOM_ENABLE);
248 if (ASIC_IS_DCE3(rdev)) 249 if (ASIC_IS_DCE3(rdev))
249 atombios_enable_crtc_memreq(crtc, 1); 250 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
250 atombios_blank_crtc(crtc, 0); 251 atombios_blank_crtc(crtc, ATOM_DISABLE);
252 /* XXX re-enable when interrupt support is added */
253 if (!ASIC_IS_DCE4(rdev))
254 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
255 radeon_crtc_load_lut(crtc);
251 break; 256 break;
252 case DRM_MODE_DPMS_STANDBY: 257 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND: 258 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF: 259 case DRM_MODE_DPMS_OFF:
255 atombios_blank_crtc(crtc, 1); 260 /* XXX re-enable when interrupt support is added */
261 if (!ASIC_IS_DCE4(rdev))
262 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
263 atombios_blank_crtc(crtc, ATOM_ENABLE);
256 if (ASIC_IS_DCE3(rdev)) 264 if (ASIC_IS_DCE3(rdev))
257 atombios_enable_crtc_memreq(crtc, 0); 265 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
258 atombios_enable_crtc(crtc, 0); 266 atombios_enable_crtc(crtc, ATOM_DISABLE);
259 break; 267 break;
260 } 268 }
261
262 if (mode != DRM_MODE_DPMS_OFF) {
263 radeon_crtc_load_lut(crtc);
264 }
265} 269}
266 270
267static void 271static void
@@ -307,7 +311,6 @@ atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 311 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id; 312 args.ucCRTC = radeon_crtc->crtc_id;
309 313
310 printk("executing set crtc dtd timing\n");
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 314 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
312} 315}
313 316
@@ -347,11 +350,58 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
347 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 350 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
348 args.ucCRTC = radeon_crtc->crtc_id; 351 args.ucCRTC = radeon_crtc->crtc_id;
349 352
350 printk("executing set crtc timing\n");
351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
352} 354}
353 355
354static void atombios_set_ss(struct drm_crtc *crtc, int enable) 356static void atombios_disable_ss(struct drm_crtc *crtc)
357{
358 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
359 struct drm_device *dev = crtc->dev;
360 struct radeon_device *rdev = dev->dev_private;
361 u32 ss_cntl;
362
363 if (ASIC_IS_DCE4(rdev)) {
364 switch (radeon_crtc->pll_id) {
365 case ATOM_PPLL1:
366 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
367 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
368 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
369 break;
370 case ATOM_PPLL2:
371 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
372 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
373 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
374 break;
375 case ATOM_DCPLL:
376 case ATOM_PPLL_INVALID:
377 return;
378 }
379 } else if (ASIC_IS_AVIVO(rdev)) {
380 switch (radeon_crtc->pll_id) {
381 case ATOM_PPLL1:
382 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
383 ss_cntl &= ~1;
384 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
385 break;
386 case ATOM_PPLL2:
387 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
388 ss_cntl &= ~1;
389 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
390 break;
391 case ATOM_DCPLL:
392 case ATOM_PPLL_INVALID:
393 return;
394 }
395 }
396}
397
398
399union atom_enable_ss {
400 ENABLE_LVDS_SS_PARAMETERS legacy;
401 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
402};
403
404static void atombios_enable_ss(struct drm_crtc *crtc)
355{ 405{
356 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 406 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
357 struct drm_device *dev = crtc->dev; 407 struct drm_device *dev = crtc->dev;
@@ -360,11 +410,14 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
360 struct radeon_encoder *radeon_encoder = NULL; 410 struct radeon_encoder *radeon_encoder = NULL;
361 struct radeon_encoder_atom_dig *dig = NULL; 411 struct radeon_encoder_atom_dig *dig = NULL;
362 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 412 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
363 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args; 413 union atom_enable_ss args;
364 ENABLE_LVDS_SS_PARAMETERS legacy_args;
365 uint16_t percentage = 0; 414 uint16_t percentage = 0;
366 uint8_t type = 0, step = 0, delay = 0, range = 0; 415 uint8_t type = 0, step = 0, delay = 0, range = 0;
367 416
417 /* XXX add ss support for DCE4 */
418 if (ASIC_IS_DCE4(rdev))
419 return;
420
368 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 421 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
369 if (encoder->crtc == crtc) { 422 if (encoder->crtc == crtc) {
370 radeon_encoder = to_radeon_encoder(encoder); 423 radeon_encoder = to_radeon_encoder(encoder);
@@ -377,9 +430,9 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
377 step = dig->ss->step; 430 step = dig->ss->step;
378 delay = dig->ss->delay; 431 delay = dig->ss->delay;
379 range = dig->ss->range; 432 range = dig->ss->range;
380 } else if (enable) 433 } else
381 return; 434 return;
382 } else if (enable) 435 } else
383 return; 436 return;
384 break; 437 break;
385 } 438 }
@@ -388,81 +441,96 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
388 if (!radeon_encoder) 441 if (!radeon_encoder)
389 return; 442 return;
390 443
444 memset(&args, 0, sizeof(args));
391 if (ASIC_IS_AVIVO(rdev)) { 445 if (ASIC_IS_AVIVO(rdev)) {
392 memset(&args, 0, sizeof(args)); 446 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
393 args.usSpreadSpectrumPercentage = cpu_to_le16(percentage); 447 args.v1.ucSpreadSpectrumType = type;
394 args.ucSpreadSpectrumType = type; 448 args.v1.ucSpreadSpectrumStep = step;
395 args.ucSpreadSpectrumStep = step; 449 args.v1.ucSpreadSpectrumDelay = delay;
396 args.ucSpreadSpectrumDelay = delay; 450 args.v1.ucSpreadSpectrumRange = range;
397 args.ucSpreadSpectrumRange = range; 451 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
398 args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 452 args.v1.ucEnable = ATOM_ENABLE;
399 args.ucEnable = enable;
400 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
401 } else { 453 } else {
402 memset(&legacy_args, 0, sizeof(legacy_args)); 454 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
403 legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage); 455 args.legacy.ucSpreadSpectrumType = type;
404 legacy_args.ucSpreadSpectrumType = type; 456 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
405 legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; 457 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
406 legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; 458 args.legacy.ucEnable = ATOM_ENABLE;
407 legacy_args.ucEnable = enable;
408 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args);
409 } 459 }
460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
410} 461}
411 462
412void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 463union adjust_pixel_clock {
464 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
465 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
466};
467
468static u32 atombios_adjust_pll(struct drm_crtc *crtc,
469 struct drm_display_mode *mode,
470 struct radeon_pll *pll)
413{ 471{
414 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
415 struct drm_device *dev = crtc->dev; 472 struct drm_device *dev = crtc->dev;
416 struct radeon_device *rdev = dev->dev_private; 473 struct radeon_device *rdev = dev->dev_private;
417 struct drm_encoder *encoder = NULL; 474 struct drm_encoder *encoder = NULL;
418 struct radeon_encoder *radeon_encoder = NULL; 475 struct radeon_encoder *radeon_encoder = NULL;
419 uint8_t frev, crev; 476 u32 adjusted_clock = mode->clock;
420 int index; 477 int encoder_mode = 0;
421 SET_PIXEL_CLOCK_PS_ALLOCATION args;
422 PIXEL_CLOCK_PARAMETERS *spc1_ptr;
423 PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
424 PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
425 uint32_t pll_clock = mode->clock;
426 uint32_t adjusted_clock;
427 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
428 struct radeon_pll *pll;
429 int pll_flags = 0;
430 478
431 memset(&args, 0, sizeof(args)); 479 /* reset the pll flags */
480 pll->flags = 0;
481
482 /* select the PLL algo */
483 if (ASIC_IS_AVIVO(rdev)) {
484 if (radeon_new_pll == 0)
485 pll->algo = PLL_ALGO_LEGACY;
486 else
487 pll->algo = PLL_ALGO_NEW;
488 } else {
489 if (radeon_new_pll == 1)
490 pll->algo = PLL_ALGO_NEW;
491 else
492 pll->algo = PLL_ALGO_LEGACY;
493 }
432 494
433 if (ASIC_IS_AVIVO(rdev)) { 495 if (ASIC_IS_AVIVO(rdev)) {
434 if ((rdev->family == CHIP_RS600) || 496 if ((rdev->family == CHIP_RS600) ||
435 (rdev->family == CHIP_RS690) || 497 (rdev->family == CHIP_RS690) ||
436 (rdev->family == CHIP_RS740)) 498 (rdev->family == CHIP_RS740))
437 pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | 499 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
438 RADEON_PLL_PREFER_CLOSEST_LOWER); 500 RADEON_PLL_PREFER_CLOSEST_LOWER);
439 501
440 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 502 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
441 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 503 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
442 else 504 else
443 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 505 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
444 } else { 506 } else {
445 pll_flags |= RADEON_PLL_LEGACY; 507 pll->flags |= RADEON_PLL_LEGACY;
446 508
447 if (mode->clock > 200000) /* range limits??? */ 509 if (mode->clock > 200000) /* range limits??? */
448 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 510 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
449 else 511 else
450 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 512 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
451 513
452 } 514 }
453 515
454 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 516 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
455 if (encoder->crtc == crtc) { 517 if (encoder->crtc == crtc) {
456 if (!ASIC_IS_AVIVO(rdev)) {
457 if (encoder->encoder_type !=
458 DRM_MODE_ENCODER_DAC)
459 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
460 if (!ASIC_IS_AVIVO(rdev)
461 && (encoder->encoder_type ==
462 DRM_MODE_ENCODER_LVDS))
463 pll_flags |= RADEON_PLL_USE_REF_DIV;
464 }
465 radeon_encoder = to_radeon_encoder(encoder); 518 radeon_encoder = to_radeon_encoder(encoder);
519 encoder_mode = atombios_get_encoder_mode(encoder);
520 if (ASIC_IS_AVIVO(rdev)) {
521 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
522 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
523 adjusted_clock = mode->clock * 2;
524 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
525 pll->algo = PLL_ALGO_LEGACY;
526 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
527 }
528 } else {
529 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
530 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
531 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
532 pll->flags |= RADEON_PLL_USE_REF_DIV;
533 }
466 break; 534 break;
467 } 535 }
468 } 536 }
@@ -472,85 +540,231 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
472 * special hw requirements. 540 * special hw requirements.
473 */ 541 */
474 if (ASIC_IS_DCE3(rdev)) { 542 if (ASIC_IS_DCE3(rdev)) {
475 ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args; 543 union adjust_pixel_clock args;
544 u8 frev, crev;
545 int index;
546
547 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
548 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
549 &crev))
550 return adjusted_clock;
551
552 memset(&args, 0, sizeof(args));
553
554 switch (frev) {
555 case 1:
556 switch (crev) {
557 case 1:
558 case 2:
559 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
560 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
561 args.v1.ucEncodeMode = encoder_mode;
562
563 atom_execute_table(rdev->mode_info.atom_context,
564 index, (uint32_t *)&args);
565 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
566 break;
567 case 3:
568 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
569 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
570 args.v3.sInput.ucEncodeMode = encoder_mode;
571 args.v3.sInput.ucDispPllConfig = 0;
572 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
573 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
574
575 if (encoder_mode == ATOM_ENCODER_MODE_DP)
576 args.v3.sInput.ucDispPllConfig |=
577 DISPPLL_CONFIG_COHERENT_MODE;
578 else {
579 if (dig->coherent_mode)
580 args.v3.sInput.ucDispPllConfig |=
581 DISPPLL_CONFIG_COHERENT_MODE;
582 if (mode->clock > 165000)
583 args.v3.sInput.ucDispPllConfig |=
584 DISPPLL_CONFIG_DUAL_LINK;
585 }
586 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
587 /* may want to enable SS on DP/eDP eventually */
588 /*args.v3.sInput.ucDispPllConfig |=
589 DISPPLL_CONFIG_SS_ENABLE;*/
590 if (encoder_mode == ATOM_ENCODER_MODE_DP)
591 args.v3.sInput.ucDispPllConfig |=
592 DISPPLL_CONFIG_COHERENT_MODE;
593 else {
594 if (mode->clock > 165000)
595 args.v3.sInput.ucDispPllConfig |=
596 DISPPLL_CONFIG_DUAL_LINK;
597 }
598 }
599 atom_execute_table(rdev->mode_info.atom_context,
600 index, (uint32_t *)&args);
601 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
602 if (args.v3.sOutput.ucRefDiv) {
603 pll->flags |= RADEON_PLL_USE_REF_DIV;
604 pll->reference_div = args.v3.sOutput.ucRefDiv;
605 }
606 if (args.v3.sOutput.ucPostDiv) {
607 pll->flags |= RADEON_PLL_USE_POST_DIV;
608 pll->post_div = args.v3.sOutput.ucPostDiv;
609 }
610 break;
611 default:
612 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
613 return adjusted_clock;
614 }
615 break;
616 default:
617 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
618 return adjusted_clock;
619 }
620 }
621 return adjusted_clock;
622}
623
624union set_pixel_clock {
625 SET_PIXEL_CLOCK_PS_ALLOCATION base;
626 PIXEL_CLOCK_PARAMETERS v1;
627 PIXEL_CLOCK_PARAMETERS_V2 v2;
628 PIXEL_CLOCK_PARAMETERS_V3 v3;
629 PIXEL_CLOCK_PARAMETERS_V5 v5;
630};
631
632static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
633{
634 struct drm_device *dev = crtc->dev;
635 struct radeon_device *rdev = dev->dev_private;
636 u8 frev, crev;
637 int index;
638 union set_pixel_clock args;
476 639
477 if (!encoder) 640 memset(&args, 0, sizeof(args));
641
642 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
643 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
644 &crev))
645 return;
646
647 switch (frev) {
648 case 1:
649 switch (crev) {
650 case 5:
651 /* if the default dcpll clock is specified,
652 * SetPixelClock provides the dividers
653 */
654 args.v5.ucCRTC = ATOM_CRTC_INVALID;
655 args.v5.usPixelClock = rdev->clock.default_dispclk;
656 args.v5.ucPpll = ATOM_DCPLL;
657 break;
658 default:
659 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
478 return; 660 return;
661 }
662 break;
663 default:
664 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
665 return;
666 }
667 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
668}
479 669
480 memset(&adjust_pll_args, 0, sizeof(adjust_pll_args)); 670static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
481 adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10); 671{
482 adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id; 672 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
483 adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder); 673 struct drm_device *dev = crtc->dev;
674 struct radeon_device *rdev = dev->dev_private;
675 struct drm_encoder *encoder = NULL;
676 struct radeon_encoder *radeon_encoder = NULL;
677 u8 frev, crev;
678 int index;
679 union set_pixel_clock args;
680 u32 pll_clock = mode->clock;
681 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
682 struct radeon_pll *pll;
683 u32 adjusted_clock;
684 int encoder_mode = 0;
484 685
485 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 686 memset(&args, 0, sizeof(args));
486 atom_execute_table(rdev->mode_info.atom_context, 687
487 index, (uint32_t *)&adjust_pll_args); 688 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
488 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10; 689 if (encoder->crtc == crtc) {
489 } else { 690 radeon_encoder = to_radeon_encoder(encoder);
490 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 691 encoder_mode = atombios_get_encoder_mode(encoder);
491 if (ASIC_IS_AVIVO(rdev) && 692 break;
492 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 693 }
493 adjusted_clock = mode->clock * 2;
494 else
495 adjusted_clock = mode->clock;
496 } 694 }
497 695
498 if (radeon_crtc->crtc_id == 0) 696 if (!radeon_encoder)
697 return;
698
699 switch (radeon_crtc->pll_id) {
700 case ATOM_PPLL1:
499 pll = &rdev->clock.p1pll; 701 pll = &rdev->clock.p1pll;
500 else 702 break;
703 case ATOM_PPLL2:
501 pll = &rdev->clock.p2pll; 704 pll = &rdev->clock.p2pll;
705 break;
706 case ATOM_DCPLL:
707 case ATOM_PPLL_INVALID:
708 pll = &rdev->clock.dcpll;
709 break;
710 }
711
712 /* adjust pixel clock as needed */
713 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
502 714
503 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 715 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
504 &ref_div, &post_div, pll_flags); 716 &ref_div, &post_div);
505 717
506 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 718 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
507 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 719 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
508 &crev); 720 &crev))
721 return;
509 722
510 switch (frev) { 723 switch (frev) {
511 case 1: 724 case 1:
512 switch (crev) { 725 switch (crev) {
513 case 1: 726 case 1:
514 spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; 727 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
515 spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 728 args.v1.usRefDiv = cpu_to_le16(ref_div);
516 spc1_ptr->usRefDiv = cpu_to_le16(ref_div); 729 args.v1.usFbDiv = cpu_to_le16(fb_div);
517 spc1_ptr->usFbDiv = cpu_to_le16(fb_div); 730 args.v1.ucFracFbDiv = frac_fb_div;
518 spc1_ptr->ucFracFbDiv = frac_fb_div; 731 args.v1.ucPostDiv = post_div;
519 spc1_ptr->ucPostDiv = post_div; 732 args.v1.ucPpll = radeon_crtc->pll_id;
520 spc1_ptr->ucPpll = 733 args.v1.ucCRTC = radeon_crtc->crtc_id;
521 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 734 args.v1.ucRefDivSrc = 1;
522 spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
523 spc1_ptr->ucRefDivSrc = 1;
524 break; 735 break;
525 case 2: 736 case 2:
526 spc2_ptr = 737 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
527 (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; 738 args.v2.usRefDiv = cpu_to_le16(ref_div);
528 spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 739 args.v2.usFbDiv = cpu_to_le16(fb_div);
529 spc2_ptr->usRefDiv = cpu_to_le16(ref_div); 740 args.v2.ucFracFbDiv = frac_fb_div;
530 spc2_ptr->usFbDiv = cpu_to_le16(fb_div); 741 args.v2.ucPostDiv = post_div;
531 spc2_ptr->ucFracFbDiv = frac_fb_div; 742 args.v2.ucPpll = radeon_crtc->pll_id;
532 spc2_ptr->ucPostDiv = post_div; 743 args.v2.ucCRTC = radeon_crtc->crtc_id;
533 spc2_ptr->ucPpll = 744 args.v2.ucRefDivSrc = 1;
534 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
535 spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
536 spc2_ptr->ucRefDivSrc = 1;
537 break; 745 break;
538 case 3: 746 case 3:
539 if (!encoder) 747 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
540 return; 748 args.v3.usRefDiv = cpu_to_le16(ref_div);
541 spc3_ptr = 749 args.v3.usFbDiv = cpu_to_le16(fb_div);
542 (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; 750 args.v3.ucFracFbDiv = frac_fb_div;
543 spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 751 args.v3.ucPostDiv = post_div;
544 spc3_ptr->usRefDiv = cpu_to_le16(ref_div); 752 args.v3.ucPpll = radeon_crtc->pll_id;
545 spc3_ptr->usFbDiv = cpu_to_le16(fb_div); 753 args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
546 spc3_ptr->ucFracFbDiv = frac_fb_div; 754 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
547 spc3_ptr->ucPostDiv = post_div; 755 args.v3.ucEncoderMode = encoder_mode;
548 spc3_ptr->ucPpll = 756 break;
549 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 757 case 5:
550 spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); 758 args.v5.ucCRTC = radeon_crtc->crtc_id;
551 spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; 759 args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
552 spc3_ptr->ucEncoderMode = 760 args.v5.ucRefDiv = ref_div;
553 atombios_get_encoder_mode(encoder); 761 args.v5.usFbDiv = cpu_to_le16(fb_div);
762 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
763 args.v5.ucPostDiv = post_div;
764 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
765 args.v5.ucTransmitterID = radeon_encoder->encoder_id;
766 args.v5.ucEncoderMode = encoder_mode;
767 args.v5.ucPpll = radeon_crtc->pll_id;
554 break; 768 break;
555 default: 769 default:
556 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 770 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
@@ -562,33 +776,177 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
562 return; 776 return;
563 } 777 }
564 778
565 printk("executing set pll\n");
566 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 779 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
567} 780}
568 781
569int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 782static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
570 struct drm_framebuffer *old_fb) 783 struct drm_framebuffer *old_fb)
571{ 784{
572 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 785 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
573 struct drm_device *dev = crtc->dev; 786 struct drm_device *dev = crtc->dev;
574 struct radeon_device *rdev = dev->dev_private; 787 struct radeon_device *rdev = dev->dev_private;
575 struct radeon_framebuffer *radeon_fb; 788 struct radeon_framebuffer *radeon_fb;
576 struct drm_gem_object *obj; 789 struct drm_gem_object *obj;
577 struct drm_radeon_gem_object *obj_priv; 790 struct radeon_bo *rbo;
578 uint64_t fb_location; 791 uint64_t fb_location;
579 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 792 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
793 int r;
580 794
581 if (!crtc->fb) 795 /* no fb bound */
582 return -EINVAL; 796 if (!crtc->fb) {
797 DRM_DEBUG("No FB bound\n");
798 return 0;
799 }
583 800
584 radeon_fb = to_radeon_framebuffer(crtc->fb); 801 radeon_fb = to_radeon_framebuffer(crtc->fb);
585 802
803 /* Pin framebuffer & get tilling informations */
586 obj = radeon_fb->obj; 804 obj = radeon_fb->obj;
587 obj_priv = obj->driver_private; 805 rbo = obj->driver_private;
806 r = radeon_bo_reserve(rbo, false);
807 if (unlikely(r != 0))
808 return r;
809 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
810 if (unlikely(r != 0)) {
811 radeon_bo_unreserve(rbo);
812 return -EINVAL;
813 }
814 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
815 radeon_bo_unreserve(rbo);
816
817 switch (crtc->fb->bits_per_pixel) {
818 case 8:
819 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
820 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
821 break;
822 case 15:
823 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
824 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
825 break;
826 case 16:
827 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
828 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
829 break;
830 case 24:
831 case 32:
832 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
833 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
834 break;
835 default:
836 DRM_ERROR("Unsupported screen depth %d\n",
837 crtc->fb->bits_per_pixel);
838 return -EINVAL;
839 }
840
841 switch (radeon_crtc->crtc_id) {
842 case 0:
843 WREG32(AVIVO_D1VGA_CONTROL, 0);
844 break;
845 case 1:
846 WREG32(AVIVO_D2VGA_CONTROL, 0);
847 break;
848 case 2:
849 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
850 break;
851 case 3:
852 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
853 break;
854 case 4:
855 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
856 break;
857 case 5:
858 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
859 break;
860 default:
861 break;
862 }
863
864 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
865 upper_32_bits(fb_location));
866 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
867 upper_32_bits(fb_location));
868 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
869 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
870 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
871 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
872 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
873
874 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
875 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
876 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
877 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
878 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
879 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
880
881 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
882 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
883 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
884
885 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
886 crtc->mode.vdisplay);
887 x &= ~3;
888 y &= ~1;
889 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
890 (x << 16) | y);
891 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
892 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
893
894 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
895 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
896 EVERGREEN_INTERLEAVE_EN);
897 else
898 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
899
900 if (old_fb && old_fb != crtc->fb) {
901 radeon_fb = to_radeon_framebuffer(old_fb);
902 rbo = radeon_fb->obj->driver_private;
903 r = radeon_bo_reserve(rbo, false);
904 if (unlikely(r != 0))
905 return r;
906 radeon_bo_unpin(rbo);
907 radeon_bo_unreserve(rbo);
908 }
909
910 /* Bytes per pixel may have changed */
911 radeon_bandwidth_update(rdev);
912
913 return 0;
914}
915
916static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
917 struct drm_framebuffer *old_fb)
918{
919 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
920 struct drm_device *dev = crtc->dev;
921 struct radeon_device *rdev = dev->dev_private;
922 struct radeon_framebuffer *radeon_fb;
923 struct drm_gem_object *obj;
924 struct radeon_bo *rbo;
925 uint64_t fb_location;
926 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
927 int r;
928
929 /* no fb bound */
930 if (!crtc->fb) {
931 DRM_DEBUG("No FB bound\n");
932 return 0;
933 }
588 934
589 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) { 935 radeon_fb = to_radeon_framebuffer(crtc->fb);
936
937 /* Pin framebuffer & get tilling informations */
938 obj = radeon_fb->obj;
939 rbo = obj->driver_private;
940 r = radeon_bo_reserve(rbo, false);
941 if (unlikely(r != 0))
942 return r;
943 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
944 if (unlikely(r != 0)) {
945 radeon_bo_unreserve(rbo);
590 return -EINVAL; 946 return -EINVAL;
591 } 947 }
948 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
949 radeon_bo_unreserve(rbo);
592 950
593 switch (crtc->fb->bits_per_pixel) { 951 switch (crtc->fb->bits_per_pixel) {
594 case 8: 952 case 8:
@@ -618,8 +976,6 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
618 return -EINVAL; 976 return -EINVAL;
619 } 977 }
620 978
621 radeon_object_get_tiling_flags(obj->driver_private,
622 &tiling_flags, NULL);
623 if (tiling_flags & RADEON_TILING_MACRO) 979 if (tiling_flags & RADEON_TILING_MACRO)
624 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 980 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
625 981
@@ -674,7 +1030,12 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
674 1030
675 if (old_fb && old_fb != crtc->fb) { 1031 if (old_fb && old_fb != crtc->fb) {
676 radeon_fb = to_radeon_framebuffer(old_fb); 1032 radeon_fb = to_radeon_framebuffer(old_fb);
677 radeon_gem_object_unpin(radeon_fb->obj); 1033 rbo = radeon_fb->obj->driver_private;
1034 r = radeon_bo_reserve(rbo, false);
1035 if (unlikely(r != 0))
1036 return r;
1037 radeon_bo_unpin(rbo);
1038 radeon_bo_unreserve(rbo);
678 } 1039 }
679 1040
680 /* Bytes per pixel may have changed */ 1041 /* Bytes per pixel may have changed */
@@ -683,6 +1044,84 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
683 return 0; 1044 return 0;
684} 1045}
685 1046
1047int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1048 struct drm_framebuffer *old_fb)
1049{
1050 struct drm_device *dev = crtc->dev;
1051 struct radeon_device *rdev = dev->dev_private;
1052
1053 if (ASIC_IS_DCE4(rdev))
1054 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1055 else if (ASIC_IS_AVIVO(rdev))
1056 return avivo_crtc_set_base(crtc, x, y, old_fb);
1057 else
1058 return radeon_crtc_set_base(crtc, x, y, old_fb);
1059}
1060
1061/* properly set additional regs when using atombios */
1062static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1063{
1064 struct drm_device *dev = crtc->dev;
1065 struct radeon_device *rdev = dev->dev_private;
1066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1067 u32 disp_merge_cntl;
1068
1069 switch (radeon_crtc->crtc_id) {
1070 case 0:
1071 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1072 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1073 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1074 break;
1075 case 1:
1076 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1077 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1078 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1079 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1080 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1081 break;
1082 }
1083}
1084
1085static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1086{
1087 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1088 struct drm_device *dev = crtc->dev;
1089 struct radeon_device *rdev = dev->dev_private;
1090 struct drm_encoder *test_encoder;
1091 struct drm_crtc *test_crtc;
1092 uint32_t pll_in_use = 0;
1093
1094 if (ASIC_IS_DCE4(rdev)) {
1095 /* if crtc is driving DP and we have an ext clock, use that */
1096 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1097 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1098 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1099 if (rdev->clock.dp_extclk)
1100 return ATOM_PPLL_INVALID;
1101 }
1102 }
1103 }
1104
1105 /* otherwise, pick one of the plls */
1106 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1107 struct radeon_crtc *radeon_test_crtc;
1108
1109 if (crtc == test_crtc)
1110 continue;
1111
1112 radeon_test_crtc = to_radeon_crtc(test_crtc);
1113 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1114 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1115 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1116 }
1117 if (!(pll_in_use & 1))
1118 return ATOM_PPLL1;
1119 return ATOM_PPLL2;
1120 } else
1121 return radeon_crtc->crtc_id;
1122
1123}
1124
686int atombios_crtc_mode_set(struct drm_crtc *crtc, 1125int atombios_crtc_mode_set(struct drm_crtc *crtc,
687 struct drm_display_mode *mode, 1126 struct drm_display_mode *mode,
688 struct drm_display_mode *adjusted_mode, 1127 struct drm_display_mode *adjusted_mode,
@@ -694,19 +1133,24 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
694 1133
695 /* TODO color tiling */ 1134 /* TODO color tiling */
696 1135
697 atombios_set_ss(crtc, 0); 1136 atombios_disable_ss(crtc);
1137 /* always set DCPLL */
1138 if (ASIC_IS_DCE4(rdev))
1139 atombios_crtc_set_dcpll(crtc);
698 atombios_crtc_set_pll(crtc, adjusted_mode); 1140 atombios_crtc_set_pll(crtc, adjusted_mode);
699 atombios_set_ss(crtc, 1); 1141 atombios_enable_ss(crtc);
700 atombios_crtc_set_timing(crtc, adjusted_mode);
701 1142
702 if (ASIC_IS_AVIVO(rdev)) 1143 if (ASIC_IS_DCE4(rdev))
703 atombios_crtc_set_base(crtc, x, y, old_fb); 1144 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1145 else if (ASIC_IS_AVIVO(rdev))
1146 atombios_crtc_set_timing(crtc, adjusted_mode);
704 else { 1147 else {
1148 atombios_crtc_set_timing(crtc, adjusted_mode);
705 if (radeon_crtc->crtc_id == 0) 1149 if (radeon_crtc->crtc_id == 0)
706 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1150 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
707 radeon_crtc_set_base(crtc, x, y, old_fb); 1151 radeon_legacy_atom_fixup(crtc);
708 radeon_legacy_atom_set_surface(crtc);
709 } 1152 }
1153 atombios_crtc_set_base(crtc, x, y, old_fb);
710 atombios_overscan_setup(crtc, mode, adjusted_mode); 1154 atombios_overscan_setup(crtc, mode, adjusted_mode);
711 atombios_scaler_setup(crtc); 1155 atombios_scaler_setup(crtc);
712 return 0; 1156 return 0;
@@ -723,14 +1167,19 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
723 1167
724static void atombios_crtc_prepare(struct drm_crtc *crtc) 1168static void atombios_crtc_prepare(struct drm_crtc *crtc)
725{ 1169{
1170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1171
1172 /* pick pll */
1173 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1174
1175 atombios_lock_crtc(crtc, ATOM_ENABLE);
726 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1176 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
727 atombios_lock_crtc(crtc, 1);
728} 1177}
729 1178
730static void atombios_crtc_commit(struct drm_crtc *crtc) 1179static void atombios_crtc_commit(struct drm_crtc *crtc)
731{ 1180{
732 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1181 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
733 atombios_lock_crtc(crtc, 0); 1182 atombios_lock_crtc(crtc, ATOM_DISABLE);
734} 1183}
735 1184
736static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1185static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
@@ -746,8 +1195,37 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
746void radeon_atombios_init_crtc(struct drm_device *dev, 1195void radeon_atombios_init_crtc(struct drm_device *dev,
747 struct radeon_crtc *radeon_crtc) 1196 struct radeon_crtc *radeon_crtc)
748{ 1197{
749 if (radeon_crtc->crtc_id == 1) 1198 struct radeon_device *rdev = dev->dev_private;
750 radeon_crtc->crtc_offset = 1199
751 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1200 if (ASIC_IS_DCE4(rdev)) {
1201 switch (radeon_crtc->crtc_id) {
1202 case 0:
1203 default:
1204 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1205 break;
1206 case 1:
1207 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1208 break;
1209 case 2:
1210 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1211 break;
1212 case 3:
1213 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1214 break;
1215 case 4:
1216 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1217 break;
1218 case 5:
1219 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1220 break;
1221 }
1222 } else {
1223 if (radeon_crtc->crtc_id == 1)
1224 radeon_crtc->crtc_offset =
1225 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1226 else
1227 radeon_crtc->crtc_offset = 0;
1228 }
1229 radeon_crtc->pll_id = -1;
752 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1230 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
753} 1231}
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-13 14:00:09 -0400