diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 14:10:23 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 15:13:15 -0400 |
commit | f45f55c4bbf8a9f9c607e5f6013abac60427e3f7 (patch) | |
tree | 17aa46b435a9708f6c8331796afdd83c750322c6 /drivers/gpu/drm/nouveau | |
parent | 0ad72863ea426d46b2786cba9430e122a40aad0b (diff) |
drm/nouveau: remove (most) hardcoded object handle usage
The PFIFO<->EVO sync buffers will be fixed up later when inter-channel
sync in general is improved.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_abi16.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_chan.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_dma.h | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_fbcon.c | 36 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv17_fence.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_fbcon.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_fbcon.c | 4 |
9 files changed, 45 insertions, 58 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index ae794625a5b8..dbba603d50c2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c | |||
@@ -301,7 +301,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) | |||
301 | if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { | 301 | if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { |
302 | init->subchan[0].handle = 0x00000000; | 302 | init->subchan[0].handle = 0x00000000; |
303 | init->subchan[0].grclass = 0x0000; | 303 | init->subchan[0].grclass = 0x0000; |
304 | init->subchan[1].handle = NvSw; | 304 | init->subchan[1].handle = chan->chan->nvsw.handle; |
305 | init->subchan[1].grclass = 0x506e; | 305 | init->subchan[1].grclass = 0x506e; |
306 | init->nr_subchan = 2; | 306 | init->nr_subchan = 2; |
307 | } | 307 | } |
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index d222875a58d5..23146ce53526 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c | |||
@@ -765,9 +765,9 @@ nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) | |||
765 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); | 765 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
766 | OUT_RING (chan, handle); | 766 | OUT_RING (chan, handle); |
767 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); | 767 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); |
768 | OUT_RING (chan, NvNotify0); | 768 | OUT_RING (chan, chan->drm->ntfy.handle); |
769 | OUT_RING (chan, NvDmaFB); | 769 | OUT_RING (chan, chan->vram.handle); |
770 | OUT_RING (chan, NvDmaFB); | 770 | OUT_RING (chan, chan->vram.handle); |
771 | } | 771 | } |
772 | 772 | ||
773 | return ret; | 773 | return ret; |
@@ -854,7 +854,7 @@ nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) | |||
854 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); | 854 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
855 | OUT_RING (chan, handle); | 855 | OUT_RING (chan, handle); |
856 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); | 856 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); |
857 | OUT_RING (chan, NvNotify0); | 857 | OUT_RING (chan, chan->drm->ntfy.handle); |
858 | } | 858 | } |
859 | 859 | ||
860 | return ret; | 860 | return ret; |
@@ -866,7 +866,7 @@ nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, | |||
866 | { | 866 | { |
867 | if (mem->mem_type == TTM_PL_TT) | 867 | if (mem->mem_type == TTM_PL_TT) |
868 | return NvDmaTT; | 868 | return NvDmaTT; |
869 | return NvDmaFB; | 869 | return chan->vram.handle; |
870 | } | 870 | } |
871 | 871 | ||
872 | static int | 872 | static int |
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 2072518f93fa..676b1b9a3086 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c | |||
@@ -335,7 +335,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) | |||
335 | 335 | ||
336 | /* allocate software object class (used for fences on <= nv05) */ | 336 | /* allocate software object class (used for fences on <= nv05) */ |
337 | if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { | 337 | if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { |
338 | ret = nvif_object_init(chan->object, NULL, NvSw, 0x006e, | 338 | ret = nvif_object_init(chan->object, NULL, 0x006e, 0x006e, |
339 | NULL, 0, &chan->nvsw); | 339 | NULL, 0, &chan->nvsw); |
340 | if (ret) | 340 | if (ret) |
341 | return ret; | 341 | return ret; |
@@ -349,7 +349,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) | |||
349 | return ret; | 349 | return ret; |
350 | 350 | ||
351 | BEGIN_NV04(chan, NvSubSw, 0x0000, 1); | 351 | BEGIN_NV04(chan, NvSubSw, 0x0000, 1); |
352 | OUT_RING (chan, NvSw); | 352 | OUT_RING (chan, chan->nvsw.handle); |
353 | FIRE_RING (chan); | 353 | FIRE_RING (chan); |
354 | } | 354 | } |
355 | 355 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 28757c3f9438..8da0a272c45a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h | |||
@@ -58,28 +58,14 @@ enum { | |||
58 | FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */ | 58 | FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */ |
59 | }; | 59 | }; |
60 | 60 | ||
61 | /* Object handles. */ | 61 | /* Object handles - for stuff that's doesn't use handle == oclass. */ |
62 | enum { | 62 | enum { |
63 | NvM2MF = 0x80000001, | ||
64 | NvDmaFB = 0x80000002, | 63 | NvDmaFB = 0x80000002, |
65 | NvDmaTT = 0x80000003, | 64 | NvDmaTT = 0x80000003, |
66 | NvNotify0 = 0x80000006, | 65 | NvNotify0 = 0x80000006, |
67 | Nv2D = 0x80000007, | ||
68 | NvCtxSurf2D = 0x80000008, | ||
69 | NvRop = 0x80000009, | ||
70 | NvImagePatt = 0x8000000a, | ||
71 | NvClipRect = 0x8000000b, | ||
72 | NvGdiRect = 0x8000000c, | ||
73 | NvImageBlit = 0x8000000d, | ||
74 | NvSw = 0x8000000e, | ||
75 | NvSema = 0x8000000f, | 66 | NvSema = 0x8000000f, |
76 | NvEvoSema0 = 0x80000010, | 67 | NvEvoSema0 = 0x80000010, |
77 | NvEvoSema1 = 0x80000011, | 68 | NvEvoSema1 = 0x80000011, |
78 | NvNotify1 = 0x80000012, | ||
79 | |||
80 | /* G80+ display objects */ | ||
81 | NvEvoVRAM = 0x01000000, | ||
82 | NvEvoSync = 0xcafe0000 | ||
83 | }; | 69 | }; |
84 | 70 | ||
85 | #define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 | 71 | #define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 |
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index b8ab117a8462..3d6735cbddf9 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c | |||
@@ -173,33 +173,33 @@ nv04_fbcon_accel_init(struct fb_info *info) | |||
173 | return -EINVAL; | 173 | return -EINVAL; |
174 | } | 174 | } |
175 | 175 | ||
176 | ret = nvif_object_init(chan->object, NULL, NvCtxSurf2D, | 176 | ret = nvif_object_init(chan->object, NULL, 0x0062, |
177 | device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ? | 177 | device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ? |
178 | 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d); | 178 | 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d); |
179 | if (ret) | 179 | if (ret) |
180 | return ret; | 180 | return ret; |
181 | 181 | ||
182 | ret = nvif_object_init(chan->object, NULL, NvClipRect, 0x0019, NULL, 0, | 182 | ret = nvif_object_init(chan->object, NULL, 0x0019, 0x0019, NULL, 0, |
183 | &nfbdev->clip); | 183 | &nfbdev->clip); |
184 | if (ret) | 184 | if (ret) |
185 | return ret; | 185 | return ret; |
186 | 186 | ||
187 | ret = nvif_object_init(chan->object, NULL, NvRop, 0x0043, NULL, 0, | 187 | ret = nvif_object_init(chan->object, NULL, 0x0043, 0x0043, NULL, 0, |
188 | &nfbdev->rop); | 188 | &nfbdev->rop); |
189 | if (ret) | 189 | if (ret) |
190 | return ret; | 190 | return ret; |
191 | 191 | ||
192 | ret = nvif_object_init(chan->object, NULL, NvImagePatt, 0x0044, NULL, 0, | 192 | ret = nvif_object_init(chan->object, NULL, 0x0044, 0x0044, NULL, 0, |
193 | &nfbdev->patt); | 193 | &nfbdev->patt); |
194 | if (ret) | 194 | if (ret) |
195 | return ret; | 195 | return ret; |
196 | 196 | ||
197 | ret = nvif_object_init(chan->object, NULL, NvGdiRect, 0x004a, NULL, 0, | 197 | ret = nvif_object_init(chan->object, NULL, 0x004a, 0x004a, NULL, 0, |
198 | &nfbdev->gdi); | 198 | &nfbdev->gdi); |
199 | if (ret) | 199 | if (ret) |
200 | return ret; | 200 | return ret; |
201 | 201 | ||
202 | ret = nvif_object_init(chan->object, NULL, NvImageBlit, | 202 | ret = nvif_object_init(chan->object, NULL, 0x005f, |
203 | device->info.chipset >= 0x11 ? 0x009f : 0x005f, | 203 | device->info.chipset >= 0x11 ? 0x009f : 0x005f, |
204 | NULL, 0, &nfbdev->blit); | 204 | NULL, 0, &nfbdev->blit); |
205 | if (ret) | 205 | if (ret) |
@@ -211,10 +211,10 @@ nv04_fbcon_accel_init(struct fb_info *info) | |||
211 | } | 211 | } |
212 | 212 | ||
213 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); | 213 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); |
214 | OUT_RING(chan, NvCtxSurf2D); | 214 | OUT_RING(chan, nfbdev->surf2d.handle); |
215 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2); | 215 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2); |
216 | OUT_RING(chan, NvDmaFB); | 216 | OUT_RING(chan, chan->vram.handle); |
217 | OUT_RING(chan, NvDmaFB); | 217 | OUT_RING(chan, chan->vram.handle); |
218 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4); | 218 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4); |
219 | OUT_RING(chan, surface_fmt); | 219 | OUT_RING(chan, surface_fmt); |
220 | OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); | 220 | OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); |
@@ -222,12 +222,12 @@ nv04_fbcon_accel_init(struct fb_info *info) | |||
222 | OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); | 222 | OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); |
223 | 223 | ||
224 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); | 224 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); |
225 | OUT_RING(chan, NvRop); | 225 | OUT_RING(chan, nfbdev->rop.handle); |
226 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1); | 226 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1); |
227 | OUT_RING(chan, 0x55); | 227 | OUT_RING(chan, 0x55); |
228 | 228 | ||
229 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); | 229 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); |
230 | OUT_RING(chan, NvImagePatt); | 230 | OUT_RING(chan, nfbdev->patt.handle); |
231 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8); | 231 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8); |
232 | OUT_RING(chan, pattern_fmt); | 232 | OUT_RING(chan, pattern_fmt); |
233 | #ifdef __BIG_ENDIAN | 233 | #ifdef __BIG_ENDIAN |
@@ -243,15 +243,15 @@ nv04_fbcon_accel_init(struct fb_info *info) | |||
243 | OUT_RING(chan, ~0); | 243 | OUT_RING(chan, ~0); |
244 | 244 | ||
245 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); | 245 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); |
246 | OUT_RING(chan, NvClipRect); | 246 | OUT_RING(chan, nfbdev->clip.handle); |
247 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2); | 247 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2); |
248 | OUT_RING(chan, 0); | 248 | OUT_RING(chan, 0); |
249 | OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); | 249 | OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); |
250 | 250 | ||
251 | BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1); | 251 | BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1); |
252 | OUT_RING(chan, NvImageBlit); | 252 | OUT_RING(chan, nfbdev->blit.handle); |
253 | BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1); | 253 | BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1); |
254 | OUT_RING(chan, NvCtxSurf2D); | 254 | OUT_RING(chan, nfbdev->surf2d.handle); |
255 | BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1); | 255 | BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1); |
256 | OUT_RING(chan, 3); | 256 | OUT_RING(chan, 3); |
257 | if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) { | 257 | if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) { |
@@ -262,12 +262,12 @@ nv04_fbcon_accel_init(struct fb_info *info) | |||
262 | } | 262 | } |
263 | 263 | ||
264 | BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1); | 264 | BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1); |
265 | OUT_RING(chan, NvGdiRect); | 265 | OUT_RING(chan, nfbdev->gdi.handle); |
266 | BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1); | 266 | BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1); |
267 | OUT_RING(chan, NvCtxSurf2D); | 267 | OUT_RING(chan, nfbdev->surf2d.handle); |
268 | BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2); | 268 | BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2); |
269 | OUT_RING(chan, NvImagePatt); | 269 | OUT_RING(chan, nfbdev->patt.handle); |
270 | OUT_RING(chan, NvRop); | 270 | OUT_RING(chan, nfbdev->rop.handle); |
271 | BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1); | 271 | BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1); |
272 | OUT_RING(chan, 1); | 272 | OUT_RING(chan, 1); |
273 | BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1); | 273 | BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1); |
diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c index 4dde5320db05..5056131731fb 100644 --- a/drivers/gpu/drm/nouveau/nv17_fence.c +++ b/drivers/gpu/drm/nouveau/nv17_fence.c | |||
@@ -35,6 +35,7 @@ nv17_fence_sync(struct nouveau_fence *fence, | |||
35 | { | 35 | { |
36 | struct nouveau_cli *cli = (void *)nvif_client(&prev->device->base); | 36 | struct nouveau_cli *cli = (void *)nvif_client(&prev->device->base); |
37 | struct nv10_fence_priv *priv = chan->drm->fence; | 37 | struct nv10_fence_priv *priv = chan->drm->fence; |
38 | struct nv10_fence_chan *fctx = chan->fence; | ||
38 | u32 value; | 39 | u32 value; |
39 | int ret; | 40 | int ret; |
40 | 41 | ||
@@ -49,7 +50,7 @@ nv17_fence_sync(struct nouveau_fence *fence, | |||
49 | ret = RING_SPACE(prev, 5); | 50 | ret = RING_SPACE(prev, 5); |
50 | if (!ret) { | 51 | if (!ret) { |
51 | BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); | 52 | BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); |
52 | OUT_RING (prev, NvSema); | 53 | OUT_RING (prev, fctx->sema.handle); |
53 | OUT_RING (prev, 0); | 54 | OUT_RING (prev, 0); |
54 | OUT_RING (prev, value + 0); | 55 | OUT_RING (prev, value + 0); |
55 | OUT_RING (prev, value + 1); | 56 | OUT_RING (prev, value + 1); |
@@ -58,7 +59,7 @@ nv17_fence_sync(struct nouveau_fence *fence, | |||
58 | 59 | ||
59 | if (!ret && !(ret = RING_SPACE(chan, 5))) { | 60 | if (!ret && !(ret = RING_SPACE(chan, 5))) { |
60 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); | 61 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); |
61 | OUT_RING (chan, NvSema); | 62 | OUT_RING (chan, fctx->sema.handle); |
62 | OUT_RING (chan, 0); | 63 | OUT_RING (chan, 0); |
63 | OUT_RING (chan, value + 1); | 64 | OUT_RING (chan, value + 1); |
64 | OUT_RING (chan, value + 2); | 65 | OUT_RING (chan, value + 2); |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index ca8c1db0ccb4..6ae03044c3dc 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -175,7 +175,7 @@ nv50_dmac_create(struct nvif_object *disp, u32 bclass, u8 head, | |||
175 | if (ret) | 175 | if (ret) |
176 | return ret; | 176 | return ret; |
177 | 177 | ||
178 | ret = nvif_object_init(&dmac->base.user, NULL, NvEvoSync, | 178 | ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000, |
179 | NV_DMA_IN_MEMORY_CLASS, | 179 | NV_DMA_IN_MEMORY_CLASS, |
180 | &(struct nv_dma_class) { | 180 | &(struct nv_dma_class) { |
181 | .flags = NV_DMA_TARGET_VRAM | | 181 | .flags = NV_DMA_TARGET_VRAM | |
@@ -187,7 +187,7 @@ nv50_dmac_create(struct nvif_object *disp, u32 bclass, u8 head, | |||
187 | if (ret) | 187 | if (ret) |
188 | return ret; | 188 | return ret; |
189 | 189 | ||
190 | ret = nvif_object_init(&dmac->base.user, NULL, NvEvoVRAM, | 190 | ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001, |
191 | NV_DMA_IN_MEMORY_CLASS, | 191 | NV_DMA_IN_MEMORY_CLASS, |
192 | &(struct nv_dma_class) { | 192 | &(struct nv_dma_class) { |
193 | .flags = NV_DMA_TARGET_VRAM | | 193 | .flags = NV_DMA_TARGET_VRAM | |
@@ -482,7 +482,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
482 | evo_data(push, sync->addr); | 482 | evo_data(push, sync->addr); |
483 | evo_data(push, sync->data++); | 483 | evo_data(push, sync->data++); |
484 | evo_data(push, sync->data); | 484 | evo_data(push, sync->data); |
485 | evo_data(push, NvEvoSync); | 485 | evo_data(push, sync->base.sync.handle); |
486 | evo_mthd(push, 0x00a0, 2); | 486 | evo_mthd(push, 0x00a0, 2); |
487 | evo_data(push, 0x00000000); | 487 | evo_data(push, 0x00000000); |
488 | evo_data(push, 0x00000000); | 488 | evo_data(push, 0x00000000); |
@@ -763,13 +763,13 @@ nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) | |||
763 | evo_data(push, 0x85000000); | 763 | evo_data(push, 0x85000000); |
764 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | 764 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
765 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | 765 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); |
766 | evo_data(push, NvEvoVRAM); | 766 | evo_data(push, mast->base.vram.handle); |
767 | } else { | 767 | } else { |
768 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); | 768 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); |
769 | evo_data(push, 0x85000000); | 769 | evo_data(push, 0x85000000); |
770 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | 770 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
771 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | 771 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); |
772 | evo_data(push, NvEvoVRAM); | 772 | evo_data(push, mast->base.vram.handle); |
773 | } | 773 | } |
774 | evo_kick(push, mast); | 774 | evo_kick(push, mast); |
775 | } | 775 | } |
@@ -887,7 +887,7 @@ nv50_crtc_commit(struct drm_crtc *crtc) | |||
887 | evo_data(push, 0xc0000000); | 887 | evo_data(push, 0xc0000000); |
888 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | 888 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); |
889 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | 889 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); |
890 | evo_data(push, NvEvoVRAM); | 890 | evo_data(push, mast->base.vram.handle); |
891 | } else { | 891 | } else { |
892 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | 892 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); |
893 | evo_data(push, nv_crtc->fb.handle); | 893 | evo_data(push, nv_crtc->fb.handle); |
@@ -897,7 +897,7 @@ nv50_crtc_commit(struct drm_crtc *crtc) | |||
897 | evo_data(push, 0x00000000); | 897 | evo_data(push, 0x00000000); |
898 | evo_data(push, 0x00000000); | 898 | evo_data(push, 0x00000000); |
899 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | 899 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); |
900 | evo_data(push, NvEvoVRAM); | 900 | evo_data(push, mast->base.vram.handle); |
901 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); | 901 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); |
902 | evo_data(push, 0xffffff00); | 902 | evo_data(push, 0xffffff00); |
903 | } | 903 | } |
@@ -2210,7 +2210,7 @@ nv50_display_init(struct drm_device *dev) | |||
2210 | } | 2210 | } |
2211 | 2211 | ||
2212 | evo_mthd(push, 0x0088, 1); | 2212 | evo_mthd(push, 0x0088, 1); |
2213 | evo_data(push, NvEvoSync); | 2213 | evo_data(push, nv50_mast(dev)->base.sync.handle); |
2214 | evo_kick(push, nv50_mast(dev)); | 2214 | evo_kick(push, nv50_mast(dev)); |
2215 | return 0; | 2215 | return 0; |
2216 | } | 2216 | } |
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index a92008c9d203..394c89abcc97 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c | |||
@@ -183,7 +183,7 @@ nv50_fbcon_accel_init(struct fb_info *info) | |||
183 | return -EINVAL; | 183 | return -EINVAL; |
184 | } | 184 | } |
185 | 185 | ||
186 | ret = nvif_object_init(chan->object, NULL, Nv2D, 0x502d, NULL, 0, | 186 | ret = nvif_object_init(chan->object, NULL, 0x502d, 0x502d, NULL, 0, |
187 | &nfbdev->twod); | 187 | &nfbdev->twod); |
188 | if (ret) | 188 | if (ret) |
189 | return ret; | 189 | return ret; |
@@ -195,11 +195,11 @@ nv50_fbcon_accel_init(struct fb_info *info) | |||
195 | } | 195 | } |
196 | 196 | ||
197 | BEGIN_NV04(chan, NvSub2D, 0x0000, 1); | 197 | BEGIN_NV04(chan, NvSub2D, 0x0000, 1); |
198 | OUT_RING(chan, Nv2D); | 198 | OUT_RING(chan, nfbdev->twod.handle); |
199 | BEGIN_NV04(chan, NvSub2D, 0x0184, 3); | 199 | BEGIN_NV04(chan, NvSub2D, 0x0184, 3); |
200 | OUT_RING(chan, NvDmaFB); | 200 | OUT_RING(chan, chan->vram.handle); |
201 | OUT_RING(chan, NvDmaFB); | 201 | OUT_RING(chan, chan->vram.handle); |
202 | OUT_RING(chan, NvDmaFB); | 202 | OUT_RING(chan, chan->vram.handle); |
203 | BEGIN_NV04(chan, NvSub2D, 0x0290, 1); | 203 | BEGIN_NV04(chan, NvSub2D, 0x0290, 1); |
204 | OUT_RING(chan, 0); | 204 | OUT_RING(chan, 0); |
205 | BEGIN_NV04(chan, NvSub2D, 0x0888, 1); | 205 | BEGIN_NV04(chan, NvSub2D, 0x0888, 1); |
diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index 93e7b697ee95..61246677e8dc 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c | |||
@@ -156,7 +156,7 @@ nvc0_fbcon_accel_init(struct fb_info *info) | |||
156 | struct nouveau_channel *chan = drm->channel; | 156 | struct nouveau_channel *chan = drm->channel; |
157 | int ret, format; | 157 | int ret, format; |
158 | 158 | ||
159 | ret = nvif_object_init(chan->object, NULL, Nv2D, 0x902d, NULL, 0, | 159 | ret = nvif_object_init(chan->object, NULL, 0x902d, 0x902d, NULL, 0, |
160 | &nfbdev->twod); | 160 | &nfbdev->twod); |
161 | if (ret) | 161 | if (ret) |
162 | return ret; | 162 | return ret; |
@@ -196,7 +196,7 @@ nvc0_fbcon_accel_init(struct fb_info *info) | |||
196 | } | 196 | } |
197 | 197 | ||
198 | BEGIN_NVC0(chan, NvSub2D, 0x0000, 1); | 198 | BEGIN_NVC0(chan, NvSub2D, 0x0000, 1); |
199 | OUT_RING (chan, 0x0000902d); | 199 | OUT_RING (chan, nfbdev->twod.handle); |
200 | BEGIN_NVC0(chan, NvSub2D, 0x0290, 1); | 200 | BEGIN_NVC0(chan, NvSub2D, 0x0290, 1); |
201 | OUT_RING (chan, 0); | 201 | OUT_RING (chan, 0); |
202 | BEGIN_NVC0(chan, NvSub2D, 0x0888, 1); | 202 | BEGIN_NVC0(chan, NvSub2D, 0x0888, 1); |