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authorIlia Mirkin <imirkin@alum.mit.edu>2014-01-16 02:47:11 -0500
committerBen Skeggs <bskeggs@redhat.com>2014-01-22 22:39:16 -0500
commite2dd003dfa81de3247d7edae5d1a49427cf5a2c4 (patch)
tree2c9494c6569a214b9cfd555b16b7d280d9d08767 /drivers/gpu/drm/nouveau
parentf87cd8b695d372087685976460fac1ec6ba2fca9 (diff)
drm/nv50/gr: add more trap names to print on error
Also avoids printing the errors bitfield if that information has already been shown. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv50.c128
1 files changed, 70 insertions, 58 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 03de5175dd9f..a489ac2f3382 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -396,6 +396,60 @@ static const struct nouveau_bitfield nv50_graph_intr_name[] = {
396 {} 396 {}
397}; 397};
398 398
399static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
400 { 0x00000004, "SURF_WIDTH_OVERRUN" },
401 { 0x00000008, "SURF_HEIGHT_OVERRUN" },
402 { 0x00000010, "DST2D_FAULT" },
403 { 0x00000020, "ZETA_FAULT" },
404 { 0x00000040, "RT_FAULT" },
405 { 0x00000080, "CUDA_FAULT" },
406 { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
407 { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
408 { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
409 { 0x00000800, "DST2D_LINEAR_MISMATCH" },
410 { 0x00001000, "RT_LINEAR_MISMATCH" },
411 {}
412};
413
414static void
415nv50_priv_prop_trap(struct nv50_graph_priv *priv,
416 u32 ustatus_addr, u32 ustatus, u32 tp)
417{
418 u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
419 u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
420 u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
421 u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
422 u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
423 u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
424 u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
425
426 /* CUDA memory: l[], g[] or stack. */
427 if (ustatus & 0x00000080) {
428 if (e18 & 0x80000000) {
429 /* g[] read fault? */
430 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
431 tp, e14, e10 | ((e18 >> 24) & 0x1f));
432 e18 &= ~0x1f000000;
433 } else if (e18 & 0xc) {
434 /* g[] write fault? */
435 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
436 tp, e14, e10 | ((e18 >> 7) & 0x1f));
437 e18 &= ~0x00000f80;
438 } else {
439 nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
440 tp, e14, e10);
441 }
442 ustatus &= ~0x00000080;
443 }
444 if (ustatus) {
445 nv_error(priv, "TRAP_PROP - TP %d -", tp);
446 nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
447 pr_cont(" - Address %02x%08x\n", e14, e10);
448 }
449 nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
450 tp, e0c, e18, e1c, e20, e24);
451}
452
399static void 453static void
400nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) 454nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
401{ 455{
@@ -469,58 +523,11 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
469 ustatus &= ~0x04030000; 523 ustatus &= ~0x04030000;
470 } 524 }
471 break; 525 break;
472 case 8: /* TPDMA error */ 526 case 8: /* PROP error */
473 { 527 if (display)
474 u32 e0c = nv_rd32(priv, ustatus_addr + 4); 528 nv50_priv_prop_trap(
475 u32 e10 = nv_rd32(priv, ustatus_addr + 8); 529 priv, ustatus_addr, ustatus, i);
476 u32 e14 = nv_rd32(priv, ustatus_addr + 0xc); 530 ustatus = 0;
477 u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
478 u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
479 u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
480 u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
481 /* 2d engine destination */
482 if (ustatus & 0x00000010) {
483 if (display) {
484 nv_error(priv, "TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
485 i, e14, e10);
486 nv_error(priv, "TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
487 i, e0c, e18, e1c, e20, e24);
488 }
489 ustatus &= ~0x00000010;
490 }
491 /* Render target */
492 if (ustatus & 0x00000040) {
493 if (display) {
494 nv_error(priv, "TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
495 i, e14, e10);
496 nv_error(priv, "TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
497 i, e0c, e18, e1c, e20, e24);
498 }
499 ustatus &= ~0x00000040;
500 }
501 /* CUDA memory: l[], g[] or stack. */
502 if (ustatus & 0x00000080) {
503 if (display) {
504 if (e18 & 0x80000000) {
505 /* g[] read fault? */
506 nv_error(priv, "TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
507 i, e14, e10 | ((e18 >> 24) & 0x1f));
508 e18 &= ~0x1f000000;
509 } else if (e18 & 0xc) {
510 /* g[] write fault? */
511 nv_error(priv, "TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
512 i, e14, e10 | ((e18 >> 7) & 0x1f));
513 e18 &= ~0x00000f80;
514 } else {
515 nv_error(priv, "TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
516 i, e14, e10);
517 }
518 nv_error(priv, "TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
519 i, e0c, e18, e1c, e20, e24);
520 }
521 ustatus &= ~0x00000080;
522 }
523 }
524 break; 531 break;
525 } 532 }
526 if (ustatus) { 533 if (ustatus) {
@@ -727,11 +734,11 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
727 status &= ~0x080; 734 status &= ~0x080;
728 } 735 }
729 736
730 /* TPDMA: Handles TP-initiated uncached memory accesses: 737 /* PROP: Handles TP-initiated uncached memory accesses:
731 * l[], g[], stack, 2d surfaces, render targets. */ 738 * l[], g[], stack, 2d surfaces, render targets. */
732 if (status & 0x100) { 739 if (status & 0x100) {
733 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, 740 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
734 "TRAP_TPDMA"); 741 "TRAP_PROP");
735 nv_wr32(priv, 0x400108, 0x100); 742 nv_wr32(priv, 0x400108, 0x100);
736 status &= ~0x100; 743 status &= ~0x100;
737 } 744 }
@@ -760,7 +767,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
760 u32 mthd = (addr & 0x00001ffc); 767 u32 mthd = (addr & 0x00001ffc);
761 u32 data = nv_rd32(priv, 0x400708); 768 u32 data = nv_rd32(priv, 0x400708);
762 u32 class = nv_rd32(priv, 0x400814); 769 u32 class = nv_rd32(priv, 0x400814);
763 u32 show = stat; 770 u32 show = stat, show_bitfield = stat;
764 int chid; 771 int chid;
765 772
766 engctx = nouveau_engctx_get(engine, inst); 773 engctx = nouveau_engctx_get(engine, inst);
@@ -778,21 +785,26 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
778 nv_error(priv, "DATA_ERROR "); 785 nv_error(priv, "DATA_ERROR ");
779 nouveau_enum_print(nv50_data_error_names, ecode); 786 nouveau_enum_print(nv50_data_error_names, ecode);
780 pr_cont("\n"); 787 pr_cont("\n");
788 show_bitfield &= ~0x00100000;
781 } 789 }
782 790
783 if (stat & 0x00200000) { 791 if (stat & 0x00200000) {
784 if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, 792 if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
785 engctx)) 793 engctx))
786 show &= ~0x00200000; 794 show &= ~0x00200000;
795 show_bitfield &= ~0x00200000;
787 } 796 }
788 797
789 nv_wr32(priv, 0x400100, stat); 798 nv_wr32(priv, 0x400100, stat);
790 nv_wr32(priv, 0x400500, 0x00010001); 799 nv_wr32(priv, 0x400500, 0x00010001);
791 800
792 if (show) { 801 if (show) {
793 nv_error(priv, "%s", ""); 802 show &= show_bitfield;
794 nouveau_bitfield_print(nv50_graph_intr_name, show); 803 if (show) {
795 pr_cont("\n"); 804 nv_error(priv, "%s", "");
805 nouveau_bitfield_print(nv50_graph_intr_name, show);
806 pr_cont("\n");
807 }
796 nv_error(priv, 808 nv_error(priv,
797 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 809 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
798 chid, (u64)inst << 12, nouveau_client_name(engctx), 810 chid, (u64)inst << 12, nouveau_client_name(engctx),
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 05:49:08 -0500