diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2011-01-10 23:23:12 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2011-01-16 20:28:31 -0500 |
commit | c693931d93facab671bafdcebf515520663c22fc (patch) | |
tree | 1b478c4367de1337c62c247653a0ef98b71fbbcf /drivers/gpu/drm/nouveau | |
parent | 07cfe0e7a820ecad078c04e9c2a102521709145d (diff) |
drm/nv40: make detection of 0x4097-ful chipsets available everywhere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv40_graph.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv40_grctx.c | 21 |
3 files changed, 20 insertions, 18 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 6d749b792088..07a7e6ad5e3b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -1574,6 +1574,20 @@ nv_match_device(struct drm_device *dev, unsigned device, | |||
1574 | dev->pdev->subsystem_device == sub_device; | 1574 | dev->pdev->subsystem_device == sub_device; |
1575 | } | 1575 | } |
1576 | 1576 | ||
1577 | /* returns 1 if device is one of the nv4x using the 0x4497 object class, | ||
1578 | * helpful to determine a number of other hardware features | ||
1579 | */ | ||
1580 | static inline int | ||
1581 | nv44_graph_class(struct drm_device *dev) | ||
1582 | { | ||
1583 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
1584 | |||
1585 | if ((dev_priv->chipset & 0xf0) == 0x60) | ||
1586 | return 1; | ||
1587 | |||
1588 | return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); | ||
1589 | } | ||
1590 | |||
1577 | /* memory type/access flags, do not match hardware values */ | 1591 | /* memory type/access flags, do not match hardware values */ |
1578 | #define NV_MEM_ACCESS_RO 1 | 1592 | #define NV_MEM_ACCESS_RO 1 |
1579 | #define NV_MEM_ACCESS_WO 2 | 1593 | #define NV_MEM_ACCESS_WO 2 |
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c index 19ef92a0375a..8870d72388c8 100644 --- a/drivers/gpu/drm/nouveau/nv40_graph.c +++ b/drivers/gpu/drm/nouveau/nv40_graph.c | |||
@@ -451,8 +451,7 @@ nv40_graph_register(struct drm_device *dev) | |||
451 | NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */ | 451 | NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */ |
452 | 452 | ||
453 | /* curie */ | 453 | /* curie */ |
454 | if (dev_priv->chipset >= 0x60 || | 454 | if (nv44_graph_class(dev)) |
455 | 0x00005450 & (1 << (dev_priv->chipset & 0x0f))) | ||
456 | NVOBJ_CLASS(dev, 0x4497, GR); | 455 | NVOBJ_CLASS(dev, 0x4497, GR); |
457 | else | 456 | else |
458 | NVOBJ_CLASS(dev, 0x4097, GR); | 457 | NVOBJ_CLASS(dev, 0x4097, GR); |
diff --git a/drivers/gpu/drm/nouveau/nv40_grctx.c b/drivers/gpu/drm/nouveau/nv40_grctx.c index ce585093264e..f70447d131d7 100644 --- a/drivers/gpu/drm/nouveau/nv40_grctx.c +++ b/drivers/gpu/drm/nouveau/nv40_grctx.c | |||
@@ -118,17 +118,6 @@ | |||
118 | */ | 118 | */ |
119 | 119 | ||
120 | static int | 120 | static int |
121 | nv40_graph_4097(struct drm_device *dev) | ||
122 | { | ||
123 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
124 | |||
125 | if ((dev_priv->chipset & 0xf0) == 0x60) | ||
126 | return 0; | ||
127 | |||
128 | return !!(0x0baf & (1 << dev_priv->chipset)); | ||
129 | } | ||
130 | |||
131 | static int | ||
132 | nv40_graph_vs_count(struct drm_device *dev) | 121 | nv40_graph_vs_count(struct drm_device *dev) |
133 | { | 122 | { |
134 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 123 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
@@ -219,7 +208,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx) | |||
219 | gr_def(ctx, 0x4009dc, 0x80000000); | 208 | gr_def(ctx, 0x4009dc, 0x80000000); |
220 | } else { | 209 | } else { |
221 | cp_ctx(ctx, 0x400840, 20); | 210 | cp_ctx(ctx, 0x400840, 20); |
222 | if (!nv40_graph_4097(ctx->dev)) { | 211 | if (nv44_graph_class(ctx->dev)) { |
223 | for (i = 0; i < 8; i++) | 212 | for (i = 0; i < 8; i++) |
224 | gr_def(ctx, 0x400860 + (i * 4), 0x00000001); | 213 | gr_def(ctx, 0x400860 + (i * 4), 0x00000001); |
225 | } | 214 | } |
@@ -228,7 +217,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx) | |||
228 | gr_def(ctx, 0x400888, 0x00000040); | 217 | gr_def(ctx, 0x400888, 0x00000040); |
229 | cp_ctx(ctx, 0x400894, 11); | 218 | cp_ctx(ctx, 0x400894, 11); |
230 | gr_def(ctx, 0x400894, 0x00000040); | 219 | gr_def(ctx, 0x400894, 0x00000040); |
231 | if (nv40_graph_4097(ctx->dev)) { | 220 | if (!nv44_graph_class(ctx->dev)) { |
232 | for (i = 0; i < 8; i++) | 221 | for (i = 0; i < 8; i++) |
233 | gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); | 222 | gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); |
234 | } | 223 | } |
@@ -546,7 +535,7 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) | |||
546 | static void | 535 | static void |
547 | nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) | 536 | nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) |
548 | { | 537 | { |
549 | int len = nv40_graph_4097(ctx->dev) ? 0x0684 : 0x0084; | 538 | int len = nv44_graph_class(ctx->dev) ? 0x0084 : 0x0684; |
550 | 539 | ||
551 | cp_out (ctx, 0x300000); | 540 | cp_out (ctx, 0x300000); |
552 | cp_lsr (ctx, len - 4); | 541 | cp_lsr (ctx, len - 4); |
@@ -582,11 +571,11 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx) | |||
582 | } else { | 571 | } else { |
583 | b0_offset = 0x1d40/4; /* 2200 */ | 572 | b0_offset = 0x1d40/4; /* 2200 */ |
584 | b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ | 573 | b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ |
585 | vs_len = nv40_graph_4097(dev) ? 0x4a40/4 : 0x4980/4; | 574 | vs_len = nv44_graph_class(dev) ? 0x4980/4 : 0x4a40/4; |
586 | } | 575 | } |
587 | 576 | ||
588 | cp_lsr(ctx, vs_len * vs_nr + 0x300/4); | 577 | cp_lsr(ctx, vs_len * vs_nr + 0x300/4); |
589 | cp_out(ctx, nv40_graph_4097(dev) ? 0x800041 : 0x800029); | 578 | cp_out(ctx, nv44_graph_class(dev) ? 0x800029 : 0x800041); |
590 | 579 | ||
591 | offset = ctx->ctxvals_pos; | 580 | offset = ctx->ctxvals_pos; |
592 | ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); | 581 | ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); |