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authorBen Skeggs <bskeggs@redhat.com>2013-12-01 22:43:09 -0500
committerBen Skeggs <bskeggs@redhat.com>2014-01-22 22:38:58 -0500
commitb655f2bb77b49a3dc69d13b3daa392ea641bec86 (patch)
treed5ce5f5a661d717ac97426f5051a76f9a4b12ea5 /drivers/gpu/drm/nouveau
parentea8b4a380d46795610d17afcdec1067b0ff5f1c3 (diff)
drm/nve0/fb/gddr5: parse bios data into struct rather than using directly
Still essentially a struct of magic values with magic names and unknown purposes. But, we will shortly need to be able to mix and match bits of the previous and next configurations to do a transition reclock, as such, we can no longer directly use the vbios data with any ease. This is probably nicer anyway in the long run, for a few reasons. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h56
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h26
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h5
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/fb.h9
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c106
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/timing.c44
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c33
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c343
10 files changed, 412 insertions, 218 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
index 5442973cfd27..c364392a51d0 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
@@ -3,6 +3,62 @@
3 3
4struct nouveau_bios; 4struct nouveau_bios;
5 5
6struct nvbios_ramcfg {
7 unsigned rammap_11_08_01:1;
8 unsigned rammap_11_08_0c:2;
9 unsigned rammap_11_08_10:1;
10 unsigned rammap_11_11_0c:2;
11
12 unsigned ramcfg_11_01_01:1;
13 unsigned ramcfg_11_01_02:1;
14 unsigned ramcfg_11_01_04:1;
15 unsigned ramcfg_11_01_08:1;
16 unsigned ramcfg_11_01_10:1;
17 unsigned ramcfg_11_01_20:1;
18 unsigned ramcfg_11_01_40:1;
19 unsigned ramcfg_11_01_80:1;
20 unsigned ramcfg_11_02_03:2;
21 unsigned ramcfg_11_02_04:1;
22 unsigned ramcfg_11_02_08:1;
23 unsigned ramcfg_11_02_10:1;
24 unsigned ramcfg_11_02_40:1;
25 unsigned ramcfg_11_02_80:1;
26 unsigned ramcfg_11_03_0f:4;
27 unsigned ramcfg_11_03_30:2;
28 unsigned ramcfg_11_03_c0:2;
29 unsigned ramcfg_11_03_f0:4;
30 unsigned ramcfg_11_04:8;
31 unsigned ramcfg_11_06:8;
32 unsigned ramcfg_11_07_02:1;
33 unsigned ramcfg_11_07_04:1;
34 unsigned ramcfg_11_07_08:1;
35 unsigned ramcfg_11_07_10:1;
36 unsigned ramcfg_11_07_40:1;
37 unsigned ramcfg_11_07_80:1;
38 unsigned ramcfg_11_08_01:1;
39 unsigned ramcfg_11_08_02:1;
40 unsigned ramcfg_11_08_04:1;
41 unsigned ramcfg_11_08_08:1;
42 unsigned ramcfg_11_08_10:1;
43 unsigned ramcfg_11_09:8;
44
45 unsigned timing[11];
46 unsigned timing_20_2e_03:2;
47 unsigned timing_20_2e_30:2;
48 unsigned timing_20_2e_c0:2;
49 unsigned timing_20_2f_03:2;
50 unsigned timing_20_2c_003f:6;
51 unsigned timing_20_2c_1fc0:7;
52 unsigned timing_20_30_f8:5;
53 unsigned timing_20_30_07:3;
54 unsigned timing_20_31_0007:3;
55 unsigned timing_20_31_0078:4;
56 unsigned timing_20_31_0780:4;
57 unsigned timing_20_31_0800:1;
58 unsigned timing_20_31_7000:3;
59 unsigned timing_20_31_8000:1;
60};
61
6u8 nvbios_ramcfg_count(struct nouveau_bios *); 62u8 nvbios_ramcfg_count(struct nouveau_bios *);
7u8 nvbios_ramcfg_index(struct nouveau_bios *); 63u8 nvbios_ramcfg_index(struct nouveau_bios *);
8 64
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
index bc15e0320877..5bdf8e4db40a 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h
@@ -1,11 +1,25 @@
1#ifndef __NVBIOS_RAMMAP_H__ 1#ifndef __NVBIOS_RAMMAP_H__
2#define __NVBIOS_RAMMAP_H__ 2#define __NVBIOS_RAMMAP_H__
3 3
4u16 nvbios_rammap_table(struct nouveau_bios *, u8 *ver, u8 *hdr, 4struct nvbios_ramcfg;
5 u8 *cnt, u8 *len, u8 *snr, u8 *ssz); 5
6u16 nvbios_rammap_entry(struct nouveau_bios *, int idx, 6u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr,
7 u8 *ver, u8 *hdr, u8 *cnt, u8 *len); 7 u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
8u16 nvbios_rammap_match(struct nouveau_bios *, u16 khz, 8
9 u8 *ver, u8 *hdr, u8 *cnt, u8 *len); 9u32 nvbios_rammapEe(struct nouveau_bios *, int idx,
10 u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
11u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz,
12 u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
13u32 nvbios_rammapEp(struct nouveau_bios *, u16 mhz,
14 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
15 struct nvbios_ramcfg *);
16
17u32 nvbios_rammapSe(struct nouveau_bios *, u32 data,
18 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
19 u8 *ver, u8 *hdr);
20u32 nvbios_rammapSp(struct nouveau_bios *, u32 data,
21 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
22 u8 *ver, u8 *hdr,
23 struct nvbios_ramcfg *);
10 24
11#endif 25#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h
index 2e814827d64d..76d914b67ab5 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h
@@ -1,9 +1,14 @@
1#ifndef __NVBIOS_TIMING_H__ 1#ifndef __NVBIOS_TIMING_H__
2#define __NVBIOS_TIMING_H__ 2#define __NVBIOS_TIMING_H__
3 3
4struct nvbios_ramcfg;
5
4u16 nvbios_timingTe(struct nouveau_bios *, 6u16 nvbios_timingTe(struct nouveau_bios *,
5 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); 7 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
6u16 nvbios_timingEe(struct nouveau_bios *, int idx, 8u16 nvbios_timingEe(struct nouveau_bios *, int idx,
7 u8 *ver, u8 *hdr, u8 *cnt, u8 *len); 9 u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
10u16 nvbios_timingEp(struct nouveau_bios *, int idx,
11 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
12 struct nvbios_ramcfg *);
8 13
9#endif 14#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
index ef7795305fe6..5ac84e97e803 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
@@ -106,6 +106,12 @@ extern struct nouveau_oclass *nvaf_fb_oclass;
106extern struct nouveau_oclass *nvc0_fb_oclass; 106extern struct nouveau_oclass *nvc0_fb_oclass;
107extern struct nouveau_oclass *nve0_fb_oclass; 107extern struct nouveau_oclass *nve0_fb_oclass;
108 108
109#include <subdev/bios/ramcfg.h>
110
111struct nouveau_ram_data {
112 struct nvbios_ramcfg bios;
113};
114
109struct nouveau_ram { 115struct nouveau_ram {
110 struct nouveau_object base; 116 struct nouveau_object base;
111 enum { 117 enum {
@@ -143,6 +149,9 @@ struct nouveau_ram {
143 u32 freq; 149 u32 freq;
144 u32 mr[16]; 150 u32 mr[16];
145 u32 mr1_nuts; 151 u32 mr1_nuts;
152
153 struct nouveau_ram_data *next;
154 struct nouveau_ram_data target;
146}; 155};
147 156
148#endif 157#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
index 916fa9d302b7..f13aeead52ac 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
@@ -24,11 +24,12 @@
24 24
25#include <subdev/bios.h> 25#include <subdev/bios.h>
26#include <subdev/bios/bit.h> 26#include <subdev/bios/bit.h>
27#include <subdev/bios/ramcfg.h>
27#include <subdev/bios/rammap.h> 28#include <subdev/bios/rammap.h>
28 29
29u16 30u32
30nvbios_rammap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, 31nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
31 u8 *cnt, u8 *len, u8 *snr, u8 *ssz) 32 u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
32{ 33{
33 struct bit_entry bit_P; 34 struct bit_entry bit_P;
34 u16 rammap = 0x0000; 35 u16 rammap = 0x0000;
@@ -57,12 +58,12 @@ nvbios_rammap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
57 return 0x0000; 58 return 0x0000;
58} 59}
59 60
60u16 61u32
61nvbios_rammap_entry(struct nouveau_bios *bios, int idx, 62nvbios_rammapEe(struct nouveau_bios *bios, int idx,
62 u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 63 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
63{ 64{
64 u8 snr, ssz; 65 u8 snr, ssz;
65 u16 rammap = nvbios_rammap_table(bios, ver, hdr, cnt, len, &snr, &ssz); 66 u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz);
66 if (rammap && idx < *cnt) { 67 if (rammap && idx < *cnt) {
67 rammap = rammap + *hdr + (idx * (*len + (snr * ssz))); 68 rammap = rammap + *hdr + (idx * (*len + (snr * ssz)));
68 *hdr = *len; 69 *hdr = *len;
@@ -73,16 +74,99 @@ nvbios_rammap_entry(struct nouveau_bios *bios, int idx,
73 return 0x0000; 74 return 0x0000;
74} 75}
75 76
76u16 77u32
77nvbios_rammap_match(struct nouveau_bios *bios, u16 khz, 78nvbios_rammapEm(struct nouveau_bios *bios, u16 khz,
78 u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 79 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
79{ 80{
80 int idx = 0; 81 int idx = 0;
81 u32 data; 82 u32 data;
82 while ((data = nvbios_rammap_entry(bios, idx++, ver, hdr, cnt, len))) { 83 while ((data = nvbios_rammapEe(bios, idx++, ver, hdr, cnt, len))) {
83 if (khz >= nv_ro16(bios, data + 0x00) && 84 if (khz >= nv_ro16(bios, data + 0x00) &&
84 khz <= nv_ro16(bios, data + 0x02)) 85 khz <= nv_ro16(bios, data + 0x02))
85 break; 86 break;
86 } 87 }
87 return data; 88 return data;
88} 89}
90
91u32
92nvbios_rammapEp(struct nouveau_bios *bios, u16 khz,
93 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
94 struct nvbios_ramcfg *p)
95{
96 u32 data = nvbios_rammapEm(bios, khz, ver, hdr, cnt, len);
97 memset(p, 0x00, sizeof(*p));
98 switch (!!data * *ver) {
99 case 0x11:
100 p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
101 p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2;
102 p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
103 p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2;
104 break;
105 default:
106 data = 0;
107 break;
108 }
109 return data;
110}
111
112u32
113nvbios_rammapSe(struct nouveau_bios *bios, u32 data,
114 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
115 u8 *ver, u8 *hdr)
116{
117 if (idx < ecnt) {
118 data = data + ehdr + (idx * elen);
119 *ver = ever;
120 *hdr = elen;
121 return data;
122 }
123 return 0;
124}
125
126u32
127nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
128 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
129 u8 *ver, u8 *hdr, struct nvbios_ramcfg *p)
130{
131 data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr);
132 switch (!!data * *ver) {
133 case 0x11:
134 p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0;
135 p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1;
136 p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2;
137 p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3;
138 p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4;
139 p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5;
140 p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6;
141 p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7;
142 p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0;
143 p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
144 p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
145 p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
146 p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
147 p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7;
148 p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
149 p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4;
150 p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6;
151 p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4;
152 p->ramcfg_11_04 = (nv_ro08(bios, data + 0x04) & 0xff) >> 0;
153 p->ramcfg_11_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
154 p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1;
155 p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2;
156 p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3;
157 p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4;
158 p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6;
159 p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7;
160 p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0;
161 p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1;
162 p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2;
163 p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3;
164 p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4;
165 p->ramcfg_11_09 = (nv_ro08(bios, data + 0x09) & 0xff) >> 0;
166 break;
167 default:
168 data = 0;
169 break;
170 }
171 return data;
172}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
index ddcc595d9a01..350d44ab2ba2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
@@ -24,6 +24,7 @@
24 24
25#include <subdev/bios.h> 25#include <subdev/bios.h>
26#include <subdev/bios/bit.h> 26#include <subdev/bios/bit.h>
27#include <subdev/bios/ramcfg.h>
27#include <subdev/bios/timing.h> 28#include <subdev/bios/timing.h>
28 29
29u16 30u16
@@ -81,3 +82,46 @@ nvbios_timingEe(struct nouveau_bios *bios, int idx,
81 } 82 }
82 return 0x0000; 83 return 0x0000;
83} 84}
85
86u16
87nvbios_timingEp(struct nouveau_bios *bios, int idx,
88 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
89 struct nvbios_ramcfg *p)
90{
91 u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
92 switch (!!data * *ver) {
93 case 0x20:
94 p->timing[0] = nv_ro32(bios, data + 0x00);
95 p->timing[1] = nv_ro32(bios, data + 0x04);
96 p->timing[2] = nv_ro32(bios, data + 0x08);
97 p->timing[3] = nv_ro32(bios, data + 0x0c);
98 p->timing[4] = nv_ro32(bios, data + 0x10);
99 p->timing[5] = nv_ro32(bios, data + 0x14);
100 p->timing[6] = nv_ro32(bios, data + 0x18);
101 p->timing[7] = nv_ro32(bios, data + 0x1c);
102 p->timing[8] = nv_ro32(bios, data + 0x20);
103 p->timing[9] = nv_ro32(bios, data + 0x24);
104 p->timing[10] = nv_ro32(bios, data + 0x28);
105 p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0;
106 p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4;
107 p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6;
108 p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0;
109 temp = nv_ro16(bios, data + 0x2c);
110 p->timing_20_2c_003f = (temp & 0x003f) >> 0;
111 p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
112 p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0;
113 p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3;
114 temp = nv_ro16(bios, data + 0x31);
115 p->timing_20_31_0007 = (temp & 0x0007) >> 0;
116 p->timing_20_31_0078 = (temp & 0x0078) >> 3;
117 p->timing_20_31_0780 = (temp & 0x0780) >> 7;
118 p->timing_20_31_0800 = (temp & 0x0800) >> 11;
119 p->timing_20_31_7000 = (temp & 0x7000) >> 12;
120 p->timing_20_31_8000 = (temp & 0x8000) >> 15;
121 break;
122 default:
123 data = 0;
124 break;
125 }
126 return data;
127}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
index f2bbe9e98bda..16f0117e8e91 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c
@@ -28,34 +28,33 @@
28int 28int
29nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts) 29nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
30{ 30{
31 struct nouveau_bios *bios = nouveau_bios(ram);
32 int pd, lf, xd, vh, vr, vo, l3; 31 int pd, lf, xd, vh, vr, vo, l3;
33 int WL, CL, WR, at[2], dt, ds; 32 int WL, CL, WR, at[2], dt, ds;
34 int rq = ram->freq < 1000000; /* XXX */ 33 int rq = ram->freq < 1000000; /* XXX */
35 34
36 switch (!!ram->ramcfg.data * ram->ramcfg.version) { 35 switch (ram->ramcfg.version) {
37 case 0x11: 36 case 0x11:
38 pd = (nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x80) >> 7; 37 pd = ram->next->bios.ramcfg_11_01_80;
39 lf = (nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x40) >> 6; 38 lf = ram->next->bios.ramcfg_11_01_40;
40 xd = !(nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x20); 39 xd = !ram->next->bios.ramcfg_11_01_20;
41 vh = (nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x10) >> 4; 40 vh = ram->next->bios.ramcfg_11_02_10;
42 vr = (nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x04) >> 2; 41 vr = ram->next->bios.ramcfg_11_02_04;
43 vo = nv_ro08(bios, ram->ramcfg.data + 0x06) & 0xff; 42 vo = ram->next->bios.ramcfg_11_06;
44 l3 = !(nv_ro08(bios, ram->ramcfg.data + 0x07) & 0x02); 43 l3 = !ram->next->bios.ramcfg_11_07_02;
45 break; 44 break;
46 default: 45 default:
47 return -ENOSYS; 46 return -ENOSYS;
48 } 47 }
49 48
50 switch (!!ram->timing.data * ram->timing.version) { 49 switch (ram->timing.version) {
51 case 0x20: 50 case 0x20:
52 WL = (nv_ro16(bios, ram->timing.data + 0x04) & 0x0f80) >> 7; 51 WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
53 CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f; 52 CL = (ram->next->bios.timing[1] & 0x0000001f);
54 WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f; 53 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
55 at[0] = (nv_ro08(bios, ram->timing.data + 0x2e) & 0xc0) >> 6; 54 at[0] = ram->next->bios.timing_20_2e_c0;
56 at[1] = (nv_ro08(bios, ram->timing.data + 0x2e) & 0x30) >> 4; 55 at[1] = ram->next->bios.timing_20_2e_30;
57 dt = nv_ro08(bios, ram->timing.data + 0x2e) & 0x03; 56 dt = ram->next->bios.timing_20_2e_03;
58 ds = nv_ro08(bios, ram->timing.data + 0x2f) & 0x03; 57 ds = ram->next->bios.timing_20_2f_03;
59 break; 58 break;
60 default: 59 default:
61 return -ENOSYS; 60 return -ENOSYS;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
index 08d3ef6c2e69..f4ae8aa46a25 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
@@ -90,8 +90,8 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
90 int ret; 90 int ret;
91 91
92 /* lookup memory config data relevant to the target frequency */ 92 /* lookup memory config data relevant to the target frequency */
93 rammap.data = nvbios_rammap_match(bios, freq / 1000, &ver, &rammap.size, 93 rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
94 &cnt, &ramcfg.size); 94 &cnt, &ramcfg.size);
95 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { 95 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
96 nv_error(pfb, "invalid/missing rammap entry\n"); 96 nv_error(pfb, "invalid/missing rammap entry\n");
97 return -EINVAL; 97 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
index 9abc625d9b52..0391b824ee76 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
@@ -144,8 +144,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
144 int ret; 144 int ret;
145 145
146 /* lookup memory config data relevant to the target frequency */ 146 /* lookup memory config data relevant to the target frequency */
147 rammap.data = nvbios_rammap_match(bios, freq / 1000, &ver, &rammap.size, 147 rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
148 &cnt, &ramcfg.size); 148 &cnt, &ramcfg.size);
149 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { 149 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
150 nv_error(pfb, "invalid/missing rammap entry\n"); 150 nv_error(pfb, "invalid/missing rammap entry\n");
151 return -EINVAL; 151 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
index 6682ec049900..8820cc1c4041 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
@@ -213,12 +213,12 @@ r1373f4_init(struct nve0_ramfuc *fuc)
213} 213}
214 214
215static void 215static void
216r1373f4_fini(struct nve0_ramfuc *fuc, u32 ramcfg) 216r1373f4_fini(struct nve0_ramfuc *fuc)
217{ 217{
218 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); 218 struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc);
219 struct nouveau_bios *bios = nouveau_bios(ram); 219 struct nouveau_ram_data *next = ram->base.next;
220 u8 v0 = (nv_ro08(bios, ramcfg + 0x03) & 0xc0) >> 6; 220 u8 v0 = next->bios.ramcfg_11_03_c0;
221 u8 v1 = (nv_ro08(bios, ramcfg + 0x03) & 0x30) >> 4; 221 u8 v1 = next->bios.ramcfg_11_03_30;
222 u32 tmp; 222 u32 tmp;
223 223
224 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 224 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
@@ -259,15 +259,12 @@ nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg,
259static int 259static int
260nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) 260nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
261{ 261{
262 struct nouveau_bios *bios = nouveau_bios(pfb);
263 struct nve0_ram *ram = (void *)pfb->ram; 262 struct nve0_ram *ram = (void *)pfb->ram;
264 struct nve0_ramfuc *fuc = &ram->fuc; 263 struct nve0_ramfuc *fuc = &ram->fuc;
265 const u32 rammap = ram->base.rammap.data; 264 struct nouveau_ram_data *next = ram->base.next;
266 const u32 ramcfg = ram->base.ramcfg.data; 265 int vc = !(next->bios.ramcfg_11_02_08);
267 const u32 timing = ram->base.timing.data; 266 int mv = 1; /*XXX: !(next->bios.ramcfg_11_02_04); */
268 int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08); 267 u32 mask, data;
269 int mv = 1; /*XXX: !(nv_ro08(bios, ramcfg + 0x02) & 0x04); */
270 u32 mask, data, i;
271 268
272 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 269 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
273 ram_wr32(fuc, 0x62c000, 0x0f0f0000); 270 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
@@ -317,28 +314,28 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
317 314
318 if (1) { 315 if (1) {
319 data |= 0x800807e0; 316 data |= 0x800807e0;
320 switch (nv_ro08(bios, ramcfg + 0x03) & 0xc0) { 317 switch (next->bios.ramcfg_11_03_c0) {
321 case 0xc0: data &= ~0x00000040; break; 318 case 3: data &= ~0x00000040; break;
322 case 0x80: data &= ~0x00000100; break; 319 case 2: data &= ~0x00000100; break;
323 case 0x40: data &= ~0x80000000; break; 320 case 1: data &= ~0x80000000; break;
324 case 0x00: data &= ~0x00000400; break; 321 case 0: data &= ~0x00000400; break;
325 } 322 }
326 323
327 switch (nv_ro08(bios, ramcfg + 0x03) & 0x30) { 324 switch (next->bios.ramcfg_11_03_30) {
328 case 0x30: data &= ~0x00000020; break; 325 case 3: data &= ~0x00000020; break;
329 case 0x20: data &= ~0x00000080; break; 326 case 2: data &= ~0x00000080; break;
330 case 0x10: data &= ~0x00080000; break; 327 case 1: data &= ~0x00080000; break;
331 case 0x00: data &= ~0x00000200; break; 328 case 0: data &= ~0x00000200; break;
332 } 329 }
333 } 330 }
334 331
335 if (nv_ro08(bios, ramcfg + 0x02) & 0x80) 332 if (next->bios.ramcfg_11_02_80)
336 mask |= 0x03000000; 333 mask |= 0x03000000;
337 if (nv_ro08(bios, ramcfg + 0x02) & 0x40) 334 if (next->bios.ramcfg_11_02_40)
338 mask |= 0x00002000; 335 mask |= 0x00002000;
339 if (nv_ro08(bios, ramcfg + 0x07) & 0x10) 336 if (next->bios.ramcfg_11_07_10)
340 mask |= 0x00004000; 337 mask |= 0x00004000;
341 if (nv_ro08(bios, ramcfg + 0x07) & 0x08) 338 if (next->bios.ramcfg_11_07_08)
342 mask |= 0x00000003; 339 mask |= 0x00000003;
343 else { 340 else {
344 mask |= 0x34000000; 341 mask |= 0x34000000;
@@ -357,12 +354,12 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
357 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 354 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
358 r1373f4_init(fuc); 355 r1373f4_init(fuc);
359 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); 356 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
360 r1373f4_fini(fuc, ramcfg); 357 r1373f4_fini(fuc);
361 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); 358 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
362 } else 359 } else
363 if (ram->from != 2 && ram->mode != 2) { 360 if (ram->from != 2 && ram->mode != 2) {
364 r1373f4_init(fuc); 361 r1373f4_init(fuc);
365 r1373f4_fini(fuc, ramcfg); 362 r1373f4_fini(fuc);
366 } 363 }
367 364
368 if (ram_have(fuc, gpioMV)) { 365 if (ram_have(fuc, gpioMV)) {
@@ -373,8 +370,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
373 } 370 }
374 } 371 }
375 372
376 if ( (nv_ro08(bios, ramcfg + 0x02) & 0x40) || 373 if ( (next->bios.ramcfg_11_02_40) ||
377 (nv_ro08(bios, ramcfg + 0x07) & 0x10)) { 374 (next->bios.ramcfg_11_07_10)) {
378 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 375 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
379 ram_nsec(fuc, 20000); 376 ram_nsec(fuc, 20000);
380 } 377 }
@@ -384,38 +381,37 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
384 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); 381 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
385 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); 382 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
386 r1373f4_init(fuc); 383 r1373f4_init(fuc);
387 r1373f4_fini(fuc, ramcfg); 384 r1373f4_fini(fuc);
388 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); 385 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
389 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); 386 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
390 } else 387 } else
391 if (ram->from == 2 && ram->mode == 2) { 388 if (ram->from == 2 && ram->mode == 2) {
392 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); 389 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
393 r1373f4_init(fuc); 390 r1373f4_init(fuc);
394 r1373f4_fini(fuc, ramcfg); 391 r1373f4_fini(fuc);
395 } 392 }
396 393
397 if (ram->mode != 2) /*XXX*/ { 394 if (ram->mode != 2) /*XXX*/ {
398 if (nv_ro08(bios, ramcfg + 0x07) & 0x40) 395 if (next->bios.ramcfg_11_07_40)
399 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); 396 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
400 } 397 }
401 398
402 data = (nv_ro08(bios, rammap + 0x11) & 0x0c) >> 2; 399 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
403 ram_wr32(fuc, 0x10f65c, 0x00000011 * data); 400 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
404 ram_wr32(fuc, 0x10f6b8, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); 401 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
405 ram_wr32(fuc, 0x10f6bc, 0x01010101 * nv_ro08(bios, ramcfg + 0x09));
406 402
407 data = nv_ro08(bios, ramcfg + 0x04); 403 if (!next->bios.ramcfg_11_07_08) {
408 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { 404 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
409 ram_wr32(fuc, 0x10f698, 0x01010101 * data); 405 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
410 ram_wr32(fuc, 0x10f69c, 0x01010101 * data);
411 } 406 }
412 407
413 if (ram->mode != 2) { 408 if (ram->mode != 2) {
414 u32 temp = ram_rd32(fuc, 0x10f694) & ~0xff00ff00; 409 u32 data = 0x01000100 * next->bios.ramcfg_11_04;
415 ram_wr32(fuc, 0x10f694, temp | (0x01000100 * data)); 410 ram_nuke(fuc, 0x10f694);
411 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
416 } 412 }
417 413
418 if (ram->mode == 2 && (nv_ro08(bios, ramcfg + 0x08) & 0x10)) 414 if (ram->mode == 2 && (next->bios.ramcfg_11_08_10))
419 data = 0x00000080; 415 data = 0x00000080;
420 else 416 else
421 data = 0x00000000; 417 data = 0x00000000;
@@ -423,19 +419,19 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
423 419
424 mask = 0x00070000; 420 mask = 0x00070000;
425 data = 0x00000000; 421 data = 0x00000000;
426 if (!(nv_ro08(bios, ramcfg + 0x02) & 0x80)) 422 if (!(next->bios.ramcfg_11_02_80))
427 data |= 0x03000000; 423 data |= 0x03000000;
428 if (!(nv_ro08(bios, ramcfg + 0x02) & 0x40)) 424 if (!(next->bios.ramcfg_11_02_40))
429 data |= 0x00002000; 425 data |= 0x00002000;
430 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x10)) 426 if (!(next->bios.ramcfg_11_07_10))
431 data |= 0x00004000; 427 data |= 0x00004000;
432 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) 428 if (!(next->bios.ramcfg_11_07_08))
433 data |= 0x00000003; 429 data |= 0x00000003;
434 else 430 else
435 data |= 0x74000000; 431 data |= 0x74000000;
436 ram_mask(fuc, 0x10f824, mask, data); 432 ram_mask(fuc, 0x10f824, mask, data);
437 433
438 if (nv_ro08(bios, ramcfg + 0x01) & 0x08) 434 if (next->bios.ramcfg_11_01_08)
439 data = 0x00000000; 435 data = 0x00000000;
440 else 436 else
441 data = 0x00001000; 437 data = 0x00001000;
@@ -446,41 +442,41 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
446 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); 442 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
447 } 443 }
448 444
449 if (nv_ro08(bios, ramcfg + 0x08) & 0x01) 445 if (next->bios.ramcfg_11_08_01)
450 data = 0x00100000; 446 data = 0x00100000;
451 else 447 else
452 data = 0x00000000; 448 data = 0x00000000;
453 ram_mask(fuc, 0x10f82c, 0x00100000, data); 449 ram_mask(fuc, 0x10f82c, 0x00100000, data);
454 450
455 data = 0x00000000; 451 data = 0x00000000;
456 if (nv_ro08(bios, ramcfg + 0x08) & 0x08) 452 if (next->bios.ramcfg_11_08_08)
457 data |= 0x00002000; 453 data |= 0x00002000;
458 if (nv_ro08(bios, ramcfg + 0x08) & 0x04) 454 if (next->bios.ramcfg_11_08_04)
459 data |= 0x00001000; 455 data |= 0x00001000;
460 if (nv_ro08(bios, ramcfg + 0x08) & 0x02) 456 if (next->bios.ramcfg_11_08_02)
461 data |= 0x00004000; 457 data |= 0x00004000;
462 ram_mask(fuc, 0x10f830, 0x00007000, data); 458 ram_mask(fuc, 0x10f830, 0x00007000, data);
463 459
464 /* PFB timing */ 460 /* PFB timing */
465 ram_mask(fuc, 0x10f248, 0xffffffff, nv_ro32(bios, timing + 0x28)); 461 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
466 ram_mask(fuc, 0x10f290, 0xffffffff, nv_ro32(bios, timing + 0x00)); 462 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
467 ram_mask(fuc, 0x10f294, 0xffffffff, nv_ro32(bios, timing + 0x04)); 463 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
468 ram_mask(fuc, 0x10f298, 0xffffffff, nv_ro32(bios, timing + 0x08)); 464 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
469 ram_mask(fuc, 0x10f29c, 0xffffffff, nv_ro32(bios, timing + 0x0c)); 465 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
470 ram_mask(fuc, 0x10f2a0, 0xffffffff, nv_ro32(bios, timing + 0x10)); 466 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
471 ram_mask(fuc, 0x10f2a4, 0xffffffff, nv_ro32(bios, timing + 0x14)); 467 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
472 ram_mask(fuc, 0x10f2a8, 0xffffffff, nv_ro32(bios, timing + 0x18)); 468 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
473 ram_mask(fuc, 0x10f2ac, 0xffffffff, nv_ro32(bios, timing + 0x1c)); 469 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
474 ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20)); 470 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
475 ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24)); 471 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
476 472
477 data = mask = 0x00000000; 473 data = mask = 0x00000000;
478 if (NOTE00(ramcfg_02_03 != 0)) { 474 if (NOTE00(ramcfg_02_03 != 0)) {
479 data |= (nv_ro08(bios, ramcfg + 0x02) & 0x03) << 8; 475 data |= (next->bios.ramcfg_11_02_03) << 8;
480 mask |= 0x00000300; 476 mask |= 0x00000300;
481 } 477 }
482 if (NOTE00(ramcfg_01_10)) { 478 if (NOTE00(ramcfg_01_10)) {
483 if (nv_ro08(bios, ramcfg + 0x01) & 0x10) 479 if (next->bios.ramcfg_11_01_10)
484 data |= 0x70000000; 480 data |= 0x70000000;
485 mask |= 0x70000000; 481 mask |= 0x70000000;
486 } 482 }
@@ -488,11 +484,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
488 484
489 data = mask = 0x00000000; 485 data = mask = 0x00000000;
490 if (NOTE00(timing_30_07 != 0)) { 486 if (NOTE00(timing_30_07 != 0)) {
491 data |= (nv_ro08(bios, timing + 0x30) & 0x07) << 28; 487 data |= (next->bios.timing_20_30_07) << 28;
492 mask |= 0x70000000; 488 mask |= 0x70000000;
493 } 489 }
494 if (NOTE00(ramcfg_01_01)) { 490 if (NOTE00(ramcfg_01_01)) {
495 if (nv_ro08(bios, ramcfg + 0x01) & 0x01) 491 if (next->bios.ramcfg_11_01_01)
496 data |= 0x00000100; 492 data |= 0x00000100;
497 mask |= 0x00000100; 493 mask |= 0x00000100;
498 } 494 }
@@ -500,11 +496,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
500 496
501 data = mask = 0x00000000; 497 data = mask = 0x00000000;
502 if (NOTE00(timing_30_07 != 0)) { 498 if (NOTE00(timing_30_07 != 0)) {
503 data |= (nv_ro08(bios, timing + 0x30) & 0x07) << 28; 499 data |= (next->bios.timing_20_30_07) << 28;
504 mask |= 0x70000000; 500 mask |= 0x70000000;
505 } 501 }
506 if (NOTE00(ramcfg_01_02)) { 502 if (NOTE00(ramcfg_01_02)) {
507 if (nv_ro08(bios, ramcfg + 0x01) & 0x02) 503 if (next->bios.ramcfg_11_01_02)
508 data |= 0x00000100; 504 data |= 0x00000100;
509 mask |= 0x00000100; 505 mask |= 0x00000100;
510 } 506 }
@@ -512,16 +508,16 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
512 508
513 mask = 0x33f00000; 509 mask = 0x33f00000;
514 data = 0x00000000; 510 data = 0x00000000;
515 if (!(nv_ro08(bios, ramcfg + 0x01) & 0x04)) 511 if (!(next->bios.ramcfg_11_01_04))
516 data |= 0x20200000; 512 data |= 0x20200000;
517 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) 513 if (!(next->bios.ramcfg_11_07_80))
518 data |= 0x12800000; 514 data |= 0x12800000;
519 /*XXX: see note above about there probably being some condition 515 /*XXX: see note above about there probably being some condition
520 * for the 10f824 stuff that uses ramcfg 3... 516 * for the 10f824 stuff that uses ramcfg 3...
521 */ 517 */
522 if ( (nv_ro08(bios, ramcfg + 0x03) & 0xf0)) { 518 if ( (next->bios.ramcfg_11_03_f0)) {
523 if (nv_ro08(bios, rammap + 0x08) & 0x0c) { 519 if (next->bios.rammap_11_08_0c) {
524 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) 520 if (!(next->bios.ramcfg_11_07_80))
525 mask |= 0x00000020; 521 mask |= 0x00000020;
526 else 522 else
527 data |= 0x00000020; 523 data |= 0x00000020;
@@ -534,16 +530,15 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
534 530
535 ram_mask(fuc, 0x10f808, mask, data); 531 ram_mask(fuc, 0x10f808, mask, data);
536 532
537 data = nv_ro08(bios, ramcfg + 0x03) & 0x0f; 533 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
538 ram_wr32(fuc, 0x10f870, 0x11111111 * data);
539 534
540 data = mask = 0x00000000; 535 data = mask = 0x00000000;
541 if (NOTE00(ramcfg_02_03 != 0)) { 536 if (NOTE00(ramcfg_02_03 != 0)) {
542 data |= nv_ro08(bios, ramcfg + 0x02) & 0x03; 537 data |= next->bios.ramcfg_11_02_03;
543 mask |= 0x00000003; 538 mask |= 0x00000003;
544 } 539 }
545 if (NOTE00(ramcfg_01_10)) { 540 if (NOTE00(ramcfg_01_10)) {
546 if (nv_ro08(bios, ramcfg + 0x01) & 0x10) 541 if (next->bios.ramcfg_11_01_10)
547 data |= 0x00000004; 542 data |= 0x00000004;
548 mask |= 0x00000004; 543 mask |= 0x00000004;
549 } 544 }
@@ -554,25 +549,21 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
554 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); 549 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
555 } 550 }
556 551
557 data = (nv_ro08(bios, timing + 0x30) & 0x07) << 8; 552 data = (next->bios.timing_20_30_07) << 8;
558 if (nv_ro08(bios, ramcfg + 0x01) & 0x01) 553 if (next->bios.ramcfg_11_01_01)
559 data |= 0x80000000; 554 data |= 0x80000000;
560 ram_mask(fuc, 0x100778, 0x00000700, data); 555 ram_mask(fuc, 0x100778, 0x00000700, data);
561 556
562 data = nv_ro16(bios, timing + 0x2c); 557 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
563 ram_mask(fuc, 0x10f250, 0x000003f0, (data & 0x003f) << 4); 558 ram_mask(fuc, 0x10f24c, 0x7f000000, next->bios.timing_20_2c_1fc0 << 24);
564 ram_mask(fuc, 0x10f24c, 0x7f000000, (data & 0x1fc0) << 18); 559 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
565
566 data = nv_ro08(bios, timing + 0x30);
567 ram_mask(fuc, 0x10f224, 0x001f0000, (data & 0xf8) << 13);
568 560
569 data = nv_ro16(bios, timing + 0x31); 561 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
570 ram_mask(fuc, 0x10fec4, 0x041e0f07, (data & 0x0800) << 15 | 562 next->bios.timing_20_31_0780 << 17 |
571 (data & 0x0780) << 10 | 563 next->bios.timing_20_31_0078 << 8 |
572 (data & 0x0078) << 5 | 564 next->bios.timing_20_31_0007);
573 (data & 0x0007)); 565 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
574 ram_mask(fuc, 0x10fec8, 0x00000027, (data & 0x8000) >> 10 | 566 next->bios.timing_20_31_7000);
575 (data & 0x7000) >> 12);
576 567
577 ram_wr32(fuc, 0x10f090, 0x4000007e); 568 ram_wr32(fuc, 0x10f090, 0x4000007e);
578 ram_nsec(fuc, 2000); 569 ram_nsec(fuc, 2000);
@@ -580,7 +571,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
580 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 571 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
581 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 572 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
582 573
583 if ((nv_ro08(bios, ramcfg + 0x08) & 0x10) && (ram->mode == 2) /*XXX*/) { 574 if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) {
584 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); 575 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
585 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ 576 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
586 ram_nsec(fuc, 1000); 577 ram_nsec(fuc, 1000);
@@ -613,8 +604,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
613 data = ram_rd32(fuc, 0x10f978); 604 data = ram_rd32(fuc, 0x10f978);
614 data &= ~0x00046144; 605 data &= ~0x00046144;
615 data |= 0x0000000b; 606 data |= 0x0000000b;
616 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { 607 if (!(next->bios.ramcfg_11_07_08)) {
617 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x04)) 608 if (!(next->bios.ramcfg_11_07_04))
618 data |= 0x0000200c; 609 data |= 0x0000200c;
619 else 610 else
620 data |= 0x00000000; 611 data |= 0x00000000;
@@ -628,11 +619,11 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
628 ram_wr32(fuc, 0x10f830, data); 619 ram_wr32(fuc, 0x10f830, data);
629 } 620 }
630 621
631 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { 622 if (!(next->bios.ramcfg_11_07_08)) {
632 data = 0x88020000; 623 data = 0x88020000;
633 if ( (nv_ro08(bios, ramcfg + 0x07) & 0x04)) 624 if ( (next->bios.ramcfg_11_07_04))
634 data |= 0x10000000; 625 data |= 0x10000000;
635 if (!(nv_ro08(bios, rammap + 0x08) & 0x10)) 626 if (!(next->bios.rammap_11_08_10))
636 data |= 0x00080000; 627 data |= 0x00080000;
637 } else { 628 } else {
638 data = 0xa40e0000; 629 data = 0xa40e0000;
@@ -654,12 +645,12 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
654 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 645 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
655 } 646 }
656 647
657 if (nv_ro08(bios, ramcfg + 0x07) & 0x02) 648 if (next->bios.ramcfg_11_07_02)
658 nve0_ram_train(fuc, 0x80020000, 0x01000000); 649 nve0_ram_train(fuc, 0x80020000, 0x01000000);
659 650
660 ram_wr32(fuc, 0x62c000, 0x0f0f0f00); 651 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
661 652
662 if (nv_ro08(bios, rammap + 0x08) & 0x01) 653 if (next->bios.rammap_11_08_01)
663 data = 0x00000800; 654 data = 0x00000800;
664 else 655 else
665 data = 0x00000000; 656 data = 0x00000000;
@@ -675,17 +666,14 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
675static int 666static int
676nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) 667nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
677{ 668{
678 struct nouveau_bios *bios = nouveau_bios(pfb);
679 struct nve0_ram *ram = (void *)pfb->ram; 669 struct nve0_ram *ram = (void *)pfb->ram;
680 struct nve0_ramfuc *fuc = &ram->fuc; 670 struct nve0_ramfuc *fuc = &ram->fuc;
681 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); 671 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
682 const u32 runk0 = ram->fN1 << 16; 672 const u32 runk0 = ram->fN1 << 16;
683 const u32 runk1 = ram->fN1; 673 const u32 runk1 = ram->fN1;
684 const u32 rammap = ram->base.rammap.data; 674 struct nouveau_ram_data *next = ram->base.next;
685 const u32 ramcfg = ram->base.ramcfg.data; 675 int vc = !(next->bios.ramcfg_11_02_08);
686 const u32 timing = ram->base.timing.data; 676 int mv = 1; /*XXX: !(next->bios.ramcfg_11_02_04); */
687 int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08);
688 int mv = 1; /*XXX: !(nv_ro08(bios, ramcfg + 0x02) & 0x04); */
689 u32 mask, data; 677 u32 mask, data;
690 678
691 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); 679 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
@@ -700,7 +688,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
700 } 688 }
701 689
702 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 690 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
703 if ((nv_ro08(bios, ramcfg + 0x03) & 0xf0)) 691 if ((next->bios.ramcfg_11_03_f0))
704 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); 692 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
705 693
706 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ 694 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
@@ -725,28 +713,28 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
725 if (1) { 713 if (1) {
726 mask |= 0x800807e0; 714 mask |= 0x800807e0;
727 data |= 0x800807e0; 715 data |= 0x800807e0;
728 switch (nv_ro08(bios, ramcfg + 0x03) & 0xc0) { 716 switch (next->bios.ramcfg_11_03_c0) {
729 case 0xc0: data &= ~0x00000040; break; 717 case 3: data &= ~0x00000040; break;
730 case 0x80: data &= ~0x00000100; break; 718 case 2: data &= ~0x00000100; break;
731 case 0x40: data &= ~0x80000000; break; 719 case 1: data &= ~0x80000000; break;
732 case 0x00: data &= ~0x00000400; break; 720 case 0: data &= ~0x00000400; break;
733 } 721 }
734 722
735 switch (nv_ro08(bios, ramcfg + 0x03) & 0x30) { 723 switch (next->bios.ramcfg_11_03_30) {
736 case 0x30: data &= ~0x00000020; break; 724 case 3: data &= ~0x00000020; break;
737 case 0x20: data &= ~0x00000080; break; 725 case 2: data &= ~0x00000080; break;
738 case 0x10: data &= ~0x00080000; break; 726 case 1: data &= ~0x00080000; break;
739 case 0x00: data &= ~0x00000200; break; 727 case 0: data &= ~0x00000200; break;
740 } 728 }
741 } 729 }
742 730
743 if (nv_ro08(bios, ramcfg + 0x02) & 0x80) 731 if (next->bios.ramcfg_11_02_80)
744 mask |= 0x03000000; 732 mask |= 0x03000000;
745 if (nv_ro08(bios, ramcfg + 0x02) & 0x40) 733 if (next->bios.ramcfg_11_02_40)
746 mask |= 0x00002000; 734 mask |= 0x00002000;
747 if (nv_ro08(bios, ramcfg + 0x07) & 0x10) 735 if (next->bios.ramcfg_11_07_10)
748 mask |= 0x00004000; 736 mask |= 0x00004000;
749 if (nv_ro08(bios, ramcfg + 0x07) & 0x08) 737 if (next->bios.ramcfg_11_07_08)
750 mask |= 0x00000003; 738 mask |= 0x00000003;
751 else 739 else
752 mask |= 0x14000000; 740 mask |= 0x14000000;
@@ -756,7 +744,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
756 744
757 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 745 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
758 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 746 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
759 data |= (nv_ro08(bios, ramcfg + 0x03) & 0x30) << 12; 747 data |= (next->bios.ramcfg_11_03_30) << 12;
760 ram_wr32(fuc, 0x1373ec, data); 748 ram_wr32(fuc, 0x1373ec, data);
761 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 749 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
762 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); 750 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
@@ -788,68 +776,67 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
788 } 776 }
789 } 777 }
790 778
791 if ( (nv_ro08(bios, ramcfg + 0x02) & 0x40) || 779 if ( (next->bios.ramcfg_11_02_40) ||
792 (nv_ro08(bios, ramcfg + 0x07) & 0x10)) { 780 (next->bios.ramcfg_11_07_10)) {
793 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 781 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
794 ram_nsec(fuc, 20000); 782 ram_nsec(fuc, 20000);
795 } 783 }
796 784
797 if (ram->mode != 2) /*XXX*/ { 785 if (ram->mode != 2) /*XXX*/ {
798 if (nv_ro08(bios, ramcfg + 0x07) & 0x40) 786 if (next->bios.ramcfg_11_07_40)
799 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); 787 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
800 } 788 }
801 789
802 data = (nv_ro08(bios, rammap + 0x11) & 0x0c) >> 2; 790 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
803 ram_wr32(fuc, 0x10f65c, 0x00000011 * data); 791 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
804 ram_wr32(fuc, 0x10f6b8, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); 792 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
805 ram_wr32(fuc, 0x10f6bc, 0x01010101 * nv_ro08(bios, ramcfg + 0x09));
806 793
807 mask = 0x00010000; 794 mask = 0x00010000;
808 data = 0x00000000; 795 data = 0x00000000;
809 if (!(nv_ro08(bios, ramcfg + 0x02) & 0x80)) 796 if (!(next->bios.ramcfg_11_02_80))
810 data |= 0x03000000; 797 data |= 0x03000000;
811 if (!(nv_ro08(bios, ramcfg + 0x02) & 0x40)) 798 if (!(next->bios.ramcfg_11_02_40))
812 data |= 0x00002000; 799 data |= 0x00002000;
813 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x10)) 800 if (!(next->bios.ramcfg_11_07_10))
814 data |= 0x00004000; 801 data |= 0x00004000;
815 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) 802 if (!(next->bios.ramcfg_11_07_08))
816 data |= 0x00000003; 803 data |= 0x00000003;
817 else 804 else
818 data |= 0x14000000; 805 data |= 0x14000000;
819 ram_mask(fuc, 0x10f824, mask, data); 806 ram_mask(fuc, 0x10f824, mask, data);
820 ram_nsec(fuc, 1000); 807 ram_nsec(fuc, 1000);
821 808
822 if (nv_ro08(bios, ramcfg + 0x08) & 0x01) 809 if (next->bios.ramcfg_11_08_01)
823 data = 0x00100000; 810 data = 0x00100000;
824 else 811 else
825 data = 0x00000000; 812 data = 0x00000000;
826 ram_mask(fuc, 0x10f82c, 0x00100000, data); 813 ram_mask(fuc, 0x10f82c, 0x00100000, data);
827 814
828 /* PFB timing */ 815 /* PFB timing */
829 ram_mask(fuc, 0x10f248, 0xffffffff, nv_ro32(bios, timing + 0x28)); 816 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
830 ram_mask(fuc, 0x10f290, 0xffffffff, nv_ro32(bios, timing + 0x00)); 817 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
831 ram_mask(fuc, 0x10f294, 0xffffffff, nv_ro32(bios, timing + 0x04)); 818 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
832 ram_mask(fuc, 0x10f298, 0xffffffff, nv_ro32(bios, timing + 0x08)); 819 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
833 ram_mask(fuc, 0x10f29c, 0xffffffff, nv_ro32(bios, timing + 0x0c)); 820 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
834 ram_mask(fuc, 0x10f2a0, 0xffffffff, nv_ro32(bios, timing + 0x10)); 821 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
835 ram_mask(fuc, 0x10f2a4, 0xffffffff, nv_ro32(bios, timing + 0x14)); 822 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
836 ram_mask(fuc, 0x10f2a8, 0xffffffff, nv_ro32(bios, timing + 0x18)); 823 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
837 ram_mask(fuc, 0x10f2ac, 0xffffffff, nv_ro32(bios, timing + 0x1c)); 824 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
838 ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20)); 825 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
839 ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24)); 826 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
840 827
841 mask = 0x33f00000; 828 mask = 0x33f00000;
842 data = 0x00000000; 829 data = 0x00000000;
843 if (!(nv_ro08(bios, ramcfg + 0x01) & 0x04)) 830 if (!(next->bios.ramcfg_11_01_04))
844 data |= 0x20200000; 831 data |= 0x20200000;
845 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) 832 if (!(next->bios.ramcfg_11_07_80))
846 data |= 0x12800000; 833 data |= 0x12800000;
847 /*XXX: see note above about there probably being some condition 834 /*XXX: see note above about there probably being some condition
848 * for the 10f824 stuff that uses ramcfg 3... 835 * for the 10f824 stuff that uses ramcfg 3...
849 */ 836 */
850 if ( (nv_ro08(bios, ramcfg + 0x03) & 0xf0)) { 837 if ( (next->bios.ramcfg_11_03_f0)) {
851 if (nv_ro08(bios, rammap + 0x08) & 0x0c) { 838 if (next->bios.rammap_11_08_0c) {
852 if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) 839 if (!(next->bios.ramcfg_11_07_80))
853 mask |= 0x00000020; 840 mask |= 0x00000020;
854 else 841 else
855 data |= 0x00000020; 842 data |= 0x00000020;
@@ -863,21 +850,16 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
863 850
864 ram_mask(fuc, 0x10f808, mask, data); 851 ram_mask(fuc, 0x10f808, mask, data);
865 852
866 data = nv_ro08(bios, ramcfg + 0x03) & 0x0f; 853 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
867 ram_wr32(fuc, 0x10f870, 0x11111111 * data);
868 854
869 data = nv_ro16(bios, timing + 0x2c); 855 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
870 ram_mask(fuc, 0x10f250, 0x000003f0, (data & 0x003f) << 4);
871 856
872 if (((nv_ro32(bios, timing + 0x2c) & 0x00001fc0) >> 6) > 857 data = (next->bios.timing[10] & 0x7f000000) >> 24;
873 ((nv_ro32(bios, timing + 0x28) & 0x7f000000) >> 24)) 858 if ( next->bios.timing_20_2c_1fc0 > data)
874 data = (nv_ro32(bios, timing + 0x2c) & 0x00001fc0) >> 6; 859 data = next->bios.timing_20_2c_1fc0;
875 else
876 data = (nv_ro32(bios, timing + 0x28) & 0x1f000000) >> 24;
877 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 860 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
878 861
879 data = nv_ro08(bios, timing + 0x30); 862 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8);
880 ram_mask(fuc, 0x10f224, 0x001f0000, (data & 0xf8) << 13);
881 863
882 ram_wr32(fuc, 0x10f090, 0x4000007f); 864 ram_wr32(fuc, 0x10f090, 0x4000007f);
883 ram_nsec(fuc, 1000); 865 ram_nsec(fuc, 1000);
@@ -919,7 +901,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
919 901
920 ram_wr32(fuc, 0x62c000, 0x0f0f0f00); 902 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
921 903
922 if (nv_ro08(bios, rammap + 0x08) & 0x01) 904 if (next->bios.rammap_11_08_01)
923 data = 0x00000800; 905 data = 0x00000800;
924 else 906 else
925 data = 0x00000000; 907 data = 0x00000000;
@@ -938,14 +920,14 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
938 struct nve0_ram *ram = (void *)pfb->ram; 920 struct nve0_ram *ram = (void *)pfb->ram;
939 struct nve0_ramfuc *fuc = &ram->fuc; 921 struct nve0_ramfuc *fuc = &ram->fuc;
940 int ret, refclk, strap, i; 922 int ret, refclk, strap, i;
941 u32 data;
942 u8 cnt, len; 923 u8 cnt, len;
943 924
944 /* lookup memory config data relevant to the target frequency */ 925 /* lookup memory config data relevant to the target frequency */
945 ram->base.rammap.data = nvbios_rammap_match(bios, freq / 1000, 926 ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000,
946 &ram->base.rammap.version, 927 &ram->base.rammap.version,
947 &ram->base.rammap.size, &cnt, 928 &ram->base.rammap.size,
948 &ram->base.ramcfg.size); 929 &cnt, &len,
930 &ram->base.target.bios);
949 if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 || 931 if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 ||
950 ram->base.rammap.size < 0x09) { 932 ram->base.rammap.size < 0x09) {
951 nv_error(pfb, "invalid/missing rammap entry\n"); 933 nv_error(pfb, "invalid/missing rammap entry\n");
@@ -953,15 +935,13 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
953 } 935 }
954 936
955 /* locate specific data set for the attached memory */ 937 /* locate specific data set for the attached memory */
956 strap = nvbios_ramcfg_index(bios); 938 ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data,
957 if (strap >= cnt) { 939 ram->base.rammap.version,
958 nv_error(pfb, "invalid ramcfg strap\n"); 940 ram->base.rammap.size, cnt, len,
959 return -EINVAL; 941 nvbios_ramcfg_index(bios),
960 } 942 &ram->base.ramcfg.version,
961 943 &ram->base.ramcfg.size,
962 ram->base.ramcfg.version = ram->base.rammap.version; 944 &ram->base.target.bios);
963 ram->base.ramcfg.data = ram->base.rammap.data + ram->base.rammap.size +
964 (ram->base.ramcfg.size * strap);
965 if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 || 945 if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 ||
966 ram->base.ramcfg.size < 0x08) { 946 ram->base.ramcfg.size < 0x08) {
967 nv_error(pfb, "invalid/missing ramcfg entry\n"); 947 nv_error(pfb, "invalid/missing ramcfg entry\n");
@@ -972,8 +952,9 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
972 strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); 952 strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00);
973 if (strap != 0xff) { 953 if (strap != 0xff) {
974 ram->base.timing.data = 954 ram->base.timing.data =
975 nvbios_timingEe(bios, strap, &ram->base.timing.version, 955 nvbios_timingEp(bios, strap, &ram->base.timing.version,
976 &ram->base.timing.size, &cnt, &len); 956 &ram->base.timing.size, &cnt, &len,
957 &ram->base.target.bios);
977 if (!ram->base.timing.data || 958 if (!ram->base.timing.data ||
978 ram->base.timing.version != 0x20 || 959 ram->base.timing.version != 0x20 ||
979 ram->base.timing.size < 0x33) { 960 ram->base.timing.size < 0x33) {
@@ -984,6 +965,8 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
984 ram->base.timing.data = 0; 965 ram->base.timing.data = 0;
985 } 966 }
986 967
968 ram->base.next = &ram->base.target;
969
987 ret = ram_init(fuc, pfb); 970 ret = ram_init(fuc, pfb);
988 if (ret) 971 if (ret)
989 return ret; 972 return ret;
@@ -1109,7 +1092,7 @@ nve0_ram_init(struct nouveau_object *object)
1109 * binary driver skips the one that's already been setup by 1092 * binary driver skips the one that's already been setup by
1110 * the init tables. 1093 * the init tables.
1111 */ 1094 */
1112 data = nvbios_rammap_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); 1095 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1113 if (!data || hdr < 0x15) 1096 if (!data || hdr < 0x15)
1114 return -EINVAL; 1097 return -EINVAL;
1115 1098
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 16:49:03 -0500