diff options
author | Dave Airlie <airlied@redhat.com> | 2014-04-01 20:31:43 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2014-04-01 22:09:09 -0400 |
commit | 2844ea3f252331cc0ecf3ae74f6226db2f580f8a (patch) | |
tree | 8e221e499662c0e768505b5fe24b9c574e92cf33 /drivers/gpu/drm/nouveau | |
parent | e3d6ddb35f6221859b6054879d186e13a3af351e (diff) | |
parent | 6efa1f2f5417e628572a75e667a9d8c63d21bd17 (diff) |
Merge branch 'primary-plane' of git://people.freedesktop.org/~robclark/linux into drm-next
Here's the latest iteration of the universal planes work, which I believe is
finally ready for merging. Aside from the minor driver patches to use the
new drm_for_each_legacy_plane() macro for plane loops, these should all have
an r-b from Rob Clark now.
Actual userspace-visibility is currently hidden behind a
drm.universal_planes module parameter so that we can do some experimental
testing of this before flipping it on universally.
* 'primary-plane' of git://people.freedesktop.org/~robclark/linux:
drm/doc: Update plane documentation and add plane helper library
drm: Allow userspace to ask for universal plane list (v2)
drm: Remove unused drm_crtc->fb
drm: Replace crtc fb with primary plane fb (v3)
drm/msm: Switch to universal plane API's
drm: Add drm_crtc_init_with_planes() (v2)
drm: Add plane type property (v2)
drm: Add drm_universal_plane_init()
drm: Add primary plane helpers (v3)
drm: Make drm_crtc_check_viewport non-static
drm/shmobile: Restrict plane loops to only operate on legacy planes
drm/i915: Restrict plane loops to only operate on overlay planes (v2)
drm/exynos: Restrict plane loops to only operate on overlay planes (v2)
drm: Add support for multiple plane types (v2)
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r-- | drivers/gpu/drm/nouveau/dispnv04/crtc.c | 20 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/dispnv04/dfp.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_display.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 17 |
4 files changed, 24 insertions, 23 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 1caef1fd139e..41be3424c906 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c | |||
@@ -239,7 +239,7 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) | |||
239 | struct drm_device *dev = crtc->dev; | 239 | struct drm_device *dev = crtc->dev; |
240 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | 240 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
241 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; | 241 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; |
242 | struct drm_framebuffer *fb = crtc->fb; | 242 | struct drm_framebuffer *fb = crtc->primary->fb; |
243 | 243 | ||
244 | /* Calculate our timings */ | 244 | /* Calculate our timings */ |
245 | int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; | 245 | int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; |
@@ -574,7 +574,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) | |||
574 | regp->CRTC[NV_CIO_CRE_86] = 0x1; | 574 | regp->CRTC[NV_CIO_CRE_86] = 0x1; |
575 | } | 575 | } |
576 | 576 | ||
577 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8; | 577 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8; |
578 | /* Enable slaved mode (called MODE_TV in nv4ref.h) */ | 578 | /* Enable slaved mode (called MODE_TV in nv4ref.h) */ |
579 | if (lvds_output || tmds_output || tv_output) | 579 | if (lvds_output || tmds_output || tv_output) |
580 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); | 580 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); |
@@ -588,7 +588,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) | |||
588 | regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | | 588 | regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | |
589 | NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | | 589 | NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | |
590 | NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; | 590 | NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; |
591 | if (crtc->fb->depth == 16) | 591 | if (crtc->primary->fb->depth == 16) |
592 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; | 592 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
593 | if (nv_device(drm->device)->chipset >= 0x11) | 593 | if (nv_device(drm->device)->chipset >= 0x11) |
594 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; | 594 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; |
@@ -609,7 +609,7 @@ static int | |||
609 | nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) | 609 | nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
610 | { | 610 | { |
611 | struct nv04_display *disp = nv04_display(crtc->dev); | 611 | struct nv04_display *disp = nv04_display(crtc->dev); |
612 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb); | 612 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); |
613 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | 613 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
614 | int ret; | 614 | int ret; |
615 | 615 | ||
@@ -808,7 +808,7 @@ nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, | |||
808 | * mark the lut values as dirty by setting depth==0, and it'll be | 808 | * mark the lut values as dirty by setting depth==0, and it'll be |
809 | * uploaded on the first mode_set_base() | 809 | * uploaded on the first mode_set_base() |
810 | */ | 810 | */ |
811 | if (!nv_crtc->base.fb) { | 811 | if (!nv_crtc->base.primary->fb) { |
812 | nv_crtc->lut.depth = 0; | 812 | nv_crtc->lut.depth = 0; |
813 | return; | 813 | return; |
814 | } | 814 | } |
@@ -832,7 +832,7 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, | |||
832 | NV_DEBUG(drm, "index %d\n", nv_crtc->index); | 832 | NV_DEBUG(drm, "index %d\n", nv_crtc->index); |
833 | 833 | ||
834 | /* no fb bound */ | 834 | /* no fb bound */ |
835 | if (!atomic && !crtc->fb) { | 835 | if (!atomic && !crtc->primary->fb) { |
836 | NV_DEBUG(drm, "No FB bound\n"); | 836 | NV_DEBUG(drm, "No FB bound\n"); |
837 | return 0; | 837 | return 0; |
838 | } | 838 | } |
@@ -844,8 +844,8 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, | |||
844 | drm_fb = passed_fb; | 844 | drm_fb = passed_fb; |
845 | fb = nouveau_framebuffer(passed_fb); | 845 | fb = nouveau_framebuffer(passed_fb); |
846 | } else { | 846 | } else { |
847 | drm_fb = crtc->fb; | 847 | drm_fb = crtc->primary->fb; |
848 | fb = nouveau_framebuffer(crtc->fb); | 848 | fb = nouveau_framebuffer(crtc->primary->fb); |
849 | } | 849 | } |
850 | 850 | ||
851 | nv_crtc->fb.offset = fb->nvbo->bo.offset; | 851 | nv_crtc->fb.offset = fb->nvbo->bo.offset; |
@@ -857,9 +857,9 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, | |||
857 | 857 | ||
858 | /* Update the framebuffer format. */ | 858 | /* Update the framebuffer format. */ |
859 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; | 859 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; |
860 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8; | 860 | regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8; |
861 | regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; | 861 | regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
862 | if (crtc->fb->depth == 16) | 862 | if (crtc->primary->fb->depth == 16) |
863 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; | 863 | regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; |
864 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); | 864 | crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); |
865 | NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, | 865 | NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, |
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c index 7fdc51e2a571..a2d669b4acf2 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c | |||
@@ -415,7 +415,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, | |||
415 | /* Output property. */ | 415 | /* Output property. */ |
416 | if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || | 416 | if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || |
417 | (nv_connector->dithering_mode == DITHERING_MODE_AUTO && | 417 | (nv_connector->dithering_mode == DITHERING_MODE_AUTO && |
418 | encoder->crtc->fb->depth > connector->display_info.bpc * 3)) { | 418 | encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) { |
419 | if (nv_device(drm->device)->chipset == 0x11) | 419 | if (nv_device(drm->device)->chipset == 0x11) |
420 | regp->dither = savep->dither | 0x00010000; | 420 | regp->dither = savep->dither | 0x00010000; |
421 | else { | 421 | else { |
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index b1547b032150..3ff030dc1ee3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c | |||
@@ -571,7 +571,7 @@ nouveau_display_suspend(struct drm_device *dev) | |||
571 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | 571 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
572 | struct nouveau_framebuffer *nouveau_fb; | 572 | struct nouveau_framebuffer *nouveau_fb; |
573 | 573 | ||
574 | nouveau_fb = nouveau_framebuffer(crtc->fb); | 574 | nouveau_fb = nouveau_framebuffer(crtc->primary->fb); |
575 | if (!nouveau_fb || !nouveau_fb->nvbo) | 575 | if (!nouveau_fb || !nouveau_fb->nvbo) |
576 | continue; | 576 | continue; |
577 | 577 | ||
@@ -598,7 +598,7 @@ nouveau_display_repin(struct drm_device *dev) | |||
598 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | 598 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
599 | struct nouveau_framebuffer *nouveau_fb; | 599 | struct nouveau_framebuffer *nouveau_fb; |
600 | 600 | ||
601 | nouveau_fb = nouveau_framebuffer(crtc->fb); | 601 | nouveau_fb = nouveau_framebuffer(crtc->primary->fb); |
602 | if (!nouveau_fb || !nouveau_fb->nvbo) | 602 | if (!nouveau_fb || !nouveau_fb->nvbo) |
603 | continue; | 603 | continue; |
604 | 604 | ||
@@ -695,7 +695,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
695 | const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; | 695 | const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; |
696 | struct drm_device *dev = crtc->dev; | 696 | struct drm_device *dev = crtc->dev; |
697 | struct nouveau_drm *drm = nouveau_drm(dev); | 697 | struct nouveau_drm *drm = nouveau_drm(dev); |
698 | struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->fb)->nvbo; | 698 | struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->primary->fb)->nvbo; |
699 | struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo; | 699 | struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo; |
700 | struct nouveau_page_flip_state *s; | 700 | struct nouveau_page_flip_state *s; |
701 | struct nouveau_channel *chan = drm->channel; | 701 | struct nouveau_channel *chan = drm->channel; |
@@ -769,7 +769,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
769 | goto fail_unreserve; | 769 | goto fail_unreserve; |
770 | 770 | ||
771 | /* Update the crtc struct and cleanup */ | 771 | /* Update the crtc struct and cleanup */ |
772 | crtc->fb = fb; | 772 | crtc->primary->fb = fb; |
773 | 773 | ||
774 | nouveau_bo_fence(old_bo, fence); | 774 | nouveau_bo_fence(old_bo, fence); |
775 | ttm_bo_unreserve(&old_bo->bo); | 775 | ttm_bo_unreserve(&old_bo->bo); |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 2dccafc6e9db..58af547b0b93 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -651,7 +651,7 @@ nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) | |||
651 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | 651 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
652 | connector = &nv_connector->base; | 652 | connector = &nv_connector->base; |
653 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | 653 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { |
654 | if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3) | 654 | if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3) |
655 | mode = DITHERING_MODE_DYNAMIC2X2; | 655 | mode = DITHERING_MODE_DYNAMIC2X2; |
656 | } else { | 656 | } else { |
657 | mode = nv_connector->dithering_mode; | 657 | mode = nv_connector->dithering_mode; |
@@ -785,7 +785,8 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) | |||
785 | 785 | ||
786 | if (update) { | 786 | if (update) { |
787 | nv50_display_flip_stop(crtc); | 787 | nv50_display_flip_stop(crtc); |
788 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | 788 | nv50_display_flip_next(crtc, crtc->primary->fb, |
789 | NULL, 1); | ||
789 | } | 790 | } |
790 | } | 791 | } |
791 | 792 | ||
@@ -1028,7 +1029,7 @@ nv50_crtc_commit(struct drm_crtc *crtc) | |||
1028 | } | 1029 | } |
1029 | 1030 | ||
1030 | nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true); | 1031 | nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true); |
1031 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | 1032 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
1032 | } | 1033 | } |
1033 | 1034 | ||
1034 | static bool | 1035 | static bool |
@@ -1042,7 +1043,7 @@ nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, | |||
1042 | static int | 1043 | static int |
1043 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) | 1044 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
1044 | { | 1045 | { |
1045 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb); | 1046 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); |
1046 | struct nv50_head *head = nv50_head(crtc); | 1047 | struct nv50_head *head = nv50_head(crtc); |
1047 | int ret; | 1048 | int ret; |
1048 | 1049 | ||
@@ -1139,7 +1140,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, | |||
1139 | nv50_crtc_set_dither(nv_crtc, false); | 1140 | nv50_crtc_set_dither(nv_crtc, false); |
1140 | nv50_crtc_set_scale(nv_crtc, false); | 1141 | nv50_crtc_set_scale(nv_crtc, false); |
1141 | nv50_crtc_set_color_vibrance(nv_crtc, false); | 1142 | nv50_crtc_set_color_vibrance(nv_crtc, false); |
1142 | nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false); | 1143 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false); |
1143 | return 0; | 1144 | return 0; |
1144 | } | 1145 | } |
1145 | 1146 | ||
@@ -1151,7 +1152,7 @@ nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |||
1151 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | 1152 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1152 | int ret; | 1153 | int ret; |
1153 | 1154 | ||
1154 | if (!crtc->fb) { | 1155 | if (!crtc->primary->fb) { |
1155 | NV_DEBUG(drm, "No FB bound\n"); | 1156 | NV_DEBUG(drm, "No FB bound\n"); |
1156 | return 0; | 1157 | return 0; |
1157 | } | 1158 | } |
@@ -1161,8 +1162,8 @@ nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |||
1161 | return ret; | 1162 | return ret; |
1162 | 1163 | ||
1163 | nv50_display_flip_stop(crtc); | 1164 | nv50_display_flip_stop(crtc); |
1164 | nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true); | 1165 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true); |
1165 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | 1166 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
1166 | return 0; | 1167 | return 0; |
1167 | } | 1168 | } |
1168 | 1169 | ||