drm/nvc0: implement crtc pll setting

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

2 files changed, 21 insertions, 4 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 274e9b66ec63..e0997d6e6d77 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -4828,7 +4828,7 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims
                 pll_lim->min_p = record[12];
                 pll_lim->max_p = record[13];
                 /* where did this go to?? */
-                if (limit_match == 0x00614100 || limit_match == 0x00614900)
+                if ((entry[0] & 0xf0) == 0x80)
                         pll_lim->refclk = 27000;
                 else
                         pll_lim->refclk = 100000;
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index 5d11ea101666..a438e56a5286 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -264,11 +264,16 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
 int
 nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
 {
-        uint32_t reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct pll_lims pll;
-        uint32_t reg1, reg2;
+        uint32_t reg, reg1, reg2;
         int ret, N1, M1, N2, M2, P;
 
+        if (dev_priv->chipset < NV_C0)
+                reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
+        else
+                reg = 0x614140 + (head * 0x800);
+
         ret = get_pll_limits(dev, reg, &pll);
         if (ret)
                 return ret;
@@ -286,7 +291,8 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
                 nv_wr32(dev, reg, 0x10000611);
                 nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1);
                 nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
-        } else {
+        } else
+        if (dev_priv->chipset < NV_C0) {
                 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
                 if (ret <= 0)
                         return 0;
@@ -298,6 +304,17 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
                 nv_wr32(dev, reg, 0x50000610);
                 nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
                 nv_wr32(dev, reg + 8, N2);
+        } else {
+                ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
+                if (ret <= 0)
+                        return 0;
+
+                NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
+                         pclk, ret, N1, N2, M1, P);
+
+                nv_mask(dev, reg + 0x0c, 0x00000000, 0x00000100);
+                nv_wr32(dev, reg + 0x04, (P << 16) | (N1 << 8) | M1);
+                nv_wr32(dev, reg + 0x10, N2 << 16);
         }
 
         return 0;