drm/nv50: fix alignment of per-channel fifo cache

GPU pointer to the structure is shifted right by 10 bits, so we need to
align to 1024 bytes, not 256.

Reported-by: Maarten Maathuis <madman2003@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 39caf167587d..32b244bcb482 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -272,7 +272,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
                         return ret;
                 ramfc = chan->ramfc->gpuobj;
 
-                ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 256,
+                ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024,
                                              0, &chan->cache);
                 if (ret)
                         return ret;